1*c67703ebSMarek Vasut /*
2*c67703ebSMarek Vasut * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
3*c67703ebSMarek Vasut *
4*c67703ebSMarek Vasut * SPDX-License-Identifier: BSD-3-Clause
5*c67703ebSMarek Vasut */
6*c67703ebSMarek Vasut
7*c67703ebSMarek Vasut #include <stdint.h>
8*c67703ebSMarek Vasut
9*c67703ebSMarek Vasut #include <common/debug.h>
10*c67703ebSMarek Vasut
11*c67703ebSMarek Vasut #include "../qos_common.h"
12*c67703ebSMarek Vasut #include "../qos_reg.h"
13*c67703ebSMarek Vasut #include "qos_init_h3_v10.h"
14*c67703ebSMarek Vasut
15*c67703ebSMarek Vasut #define RCAR_QOS_VERSION "rev.0.36"
16*c67703ebSMarek Vasut
17*c67703ebSMarek Vasut #include "qos_init_h3_v10_mstat.h"
18*c67703ebSMarek Vasut
qos_init_h3_v10(void)19*c67703ebSMarek Vasut void qos_init_h3_v10(void)
20*c67703ebSMarek Vasut {
21*c67703ebSMarek Vasut /* DRAM Split Address mapping */
22*c67703ebSMarek Vasut #if (RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_4CH) || \
23*c67703ebSMarek Vasut (RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_AUTO)
24*c67703ebSMarek Vasut NOTICE("BL2: DRAM Split is 4ch\n");
25*c67703ebSMarek Vasut io_write_32(AXI_ADSPLCR0, ADSPLCR0_ADRMODE_DEFAULT
26*c67703ebSMarek Vasut | ADSPLCR0_SPLITSEL(0xFFU)
27*c67703ebSMarek Vasut | ADSPLCR0_AREA(0x1BU)
28*c67703ebSMarek Vasut | ADSPLCR0_SWP);
29*c67703ebSMarek Vasut io_write_32(AXI_ADSPLCR1, 0x00000000U);
30*c67703ebSMarek Vasut io_write_32(AXI_ADSPLCR2, 0xA8A90000U);
31*c67703ebSMarek Vasut io_write_32(AXI_ADSPLCR3, 0x00000000U);
32*c67703ebSMarek Vasut #elif RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_2CH
33*c67703ebSMarek Vasut NOTICE("BL2: DRAM Split is 2ch\n");
34*c67703ebSMarek Vasut io_write_32(AXI_ADSPLCR0, 0x00000000U);
35*c67703ebSMarek Vasut io_write_32(AXI_ADSPLCR1, ADSPLCR0_ADRMODE_DEFAULT
36*c67703ebSMarek Vasut | ADSPLCR0_SPLITSEL(0xFFU)
37*c67703ebSMarek Vasut | ADSPLCR0_AREA(0x1BU)
38*c67703ebSMarek Vasut | ADSPLCR0_SWP);
39*c67703ebSMarek Vasut io_write_32(AXI_ADSPLCR2, 0x00000000U);
40*c67703ebSMarek Vasut io_write_32(AXI_ADSPLCR3, 0x00000000U);
41*c67703ebSMarek Vasut #else
42*c67703ebSMarek Vasut NOTICE("BL2: DRAM Split is OFF\n");
43*c67703ebSMarek Vasut #endif
44*c67703ebSMarek Vasut
45*c67703ebSMarek Vasut #if !(RCAR_QOS_TYPE == RCAR_QOS_NONE)
46*c67703ebSMarek Vasut #if RCAR_QOS_TYPE == RCAR_QOS_TYPE_DEFAULT
47*c67703ebSMarek Vasut NOTICE("BL2: QoS is default setting(%s)\n", RCAR_QOS_VERSION);
48*c67703ebSMarek Vasut #endif
49*c67703ebSMarek Vasut
50*c67703ebSMarek Vasut /* AR Cache setting */
51*c67703ebSMarek Vasut io_write_32(0xE67D1000U, 0x00000100U);
52*c67703ebSMarek Vasut io_write_32(0xE67D1008U, 0x00000100U);
53*c67703ebSMarek Vasut
54*c67703ebSMarek Vasut /* Resource Alloc setting */
55*c67703ebSMarek Vasut io_write_32(QOSCTRL_RAS, 0x00000040U);
56*c67703ebSMarek Vasut io_write_32(QOSCTRL_FIXTH, 0x000F0005U);
57*c67703ebSMarek Vasut io_write_32(QOSCTRL_REGGD, 0x00000004U);
58*c67703ebSMarek Vasut io_write_64(QOSCTRL_DANN, 0x0202000004040404UL);
59*c67703ebSMarek Vasut io_write_32(QOSCTRL_DANT, 0x003C1110U);
60*c67703ebSMarek Vasut io_write_32(QOSCTRL_EC, 0x00080001U); /* need for H3 v1.* */
61*c67703ebSMarek Vasut io_write_64(QOSCTRL_EMS, 0x0000000000000000UL);
62*c67703ebSMarek Vasut io_write_32(QOSCTRL_INSFC, 0xC7840001U);
63*c67703ebSMarek Vasut io_write_32(QOSCTRL_BERR, 0x00000000U);
64*c67703ebSMarek Vasut
65*c67703ebSMarek Vasut /* QOSBW setting */
66*c67703ebSMarek Vasut io_write_32(QOSCTRL_SL_INIT,
67*c67703ebSMarek Vasut SL_INIT_REFFSSLOT | SL_INIT_SLOTSSLOT | SL_INIT_SSLOTCLK);
68*c67703ebSMarek Vasut io_write_32(QOSCTRL_REF_ARS, 0x00330000U);
69*c67703ebSMarek Vasut
70*c67703ebSMarek Vasut /* QOSBW SRAM setting */
71*c67703ebSMarek Vasut uint32_t i;
72*c67703ebSMarek Vasut
73*c67703ebSMarek Vasut for (i = 0U; i < ARRAY_SIZE(mstat_fix); i++) {
74*c67703ebSMarek Vasut io_write_64(QOSBW_FIX_QOS_BANK0 + i * 8, mstat_fix[i]);
75*c67703ebSMarek Vasut io_write_64(QOSBW_FIX_QOS_BANK1 + i * 8, mstat_fix[i]);
76*c67703ebSMarek Vasut }
77*c67703ebSMarek Vasut for (i = 0U; i < ARRAY_SIZE(mstat_be); i++) {
78*c67703ebSMarek Vasut io_write_64(QOSBW_BE_QOS_BANK0 + i * 8, mstat_be[i]);
79*c67703ebSMarek Vasut io_write_64(QOSBW_BE_QOS_BANK1 + i * 8, mstat_be[i]);
80*c67703ebSMarek Vasut }
81*c67703ebSMarek Vasut
82*c67703ebSMarek Vasut /* 3DG bus Leaf setting */
83*c67703ebSMarek Vasut io_write_32(0xFD820808U, 0x00001234U);
84*c67703ebSMarek Vasut io_write_32(0xFD820800U, 0x0000003FU);
85*c67703ebSMarek Vasut io_write_32(0xFD821800U, 0x0000003FU);
86*c67703ebSMarek Vasut io_write_32(0xFD822800U, 0x0000003FU);
87*c67703ebSMarek Vasut io_write_32(0xFD823800U, 0x0000003FU);
88*c67703ebSMarek Vasut io_write_32(0xFD824800U, 0x0000003FU);
89*c67703ebSMarek Vasut io_write_32(0xFD825800U, 0x0000003FU);
90*c67703ebSMarek Vasut io_write_32(0xFD826800U, 0x0000003FU);
91*c67703ebSMarek Vasut io_write_32(0xFD827800U, 0x0000003FU);
92*c67703ebSMarek Vasut
93*c67703ebSMarek Vasut /* Resource Alloc start */
94*c67703ebSMarek Vasut io_write_32(QOSCTRL_RAEN, 0x00000001U);
95*c67703ebSMarek Vasut
96*c67703ebSMarek Vasut /* QOSBW start */
97*c67703ebSMarek Vasut io_write_32(QOSCTRL_STATQC, 0x00000001U);
98*c67703ebSMarek Vasut #else
99*c67703ebSMarek Vasut NOTICE("BL2: QoS is None\n");
100*c67703ebSMarek Vasut
101*c67703ebSMarek Vasut /* Resource Alloc setting */
102*c67703ebSMarek Vasut io_write_32(QOSCTRL_EC, 0x00080001U); /* need for H3 v1.* */
103*c67703ebSMarek Vasut #endif /* !(RCAR_QOS_TYPE == RCAR_QOS_NONE) */
104*c67703ebSMarek Vasut }
105