| /rk3399_ARM-atf/plat/xilinx/zynqmp/include/ |
| H A D | plat_pm_common.h | 8ce93ec9531c4b7da2d25f2e3957ca13204a3ac1 Mon Jul 28 05:56:33 UTC 2025 Ronak Jain <ronak.jain@amd.com> feat(zynqmp): mark IPI calls secure/non-secure
Use BIT24 of the IPI command header from payload[0] to identify the
caller's security state. If the SMC caller is non-secure, set BIT24
to indicate a non-secure origin.
The mechanism is already present in Versal, Versal NET, and
Versal Gen 2 platforms. Extend the same support to Zynq UltraScale+
MPSoC (ZU+) to align its behavior with newer SoCs.
Change-Id: Ic77926033e76a53c0fa1a9949e6838ec64bd6ae5
Signed-off-by: Ronak Jain <ronak.jain@amd.com>
|
| /rk3399_ARM-atf/plat/xilinx/zynqmp/pm_service/ |
| H A D | zynqmp_pm_api_sys.h | 8ce93ec9531c4b7da2d25f2e3957ca13204a3ac1 Mon Jul 28 05:56:33 UTC 2025 Ronak Jain <ronak.jain@amd.com> feat(zynqmp): mark IPI calls secure/non-secure
Use BIT24 of the IPI command header from payload[0] to identify the
caller's security state. If the SMC caller is non-secure, set BIT24
to indicate a non-secure origin.
The mechanism is already present in Versal, Versal NET, and
Versal Gen 2 platforms. Extend the same support to Zynq UltraScale+
MPSoC (ZU+) to align its behavior with newer SoCs.
Change-Id: Ic77926033e76a53c0fa1a9949e6838ec64bd6ae5
Signed-off-by: Ronak Jain <ronak.jain@amd.com>
|
| H A D | pm_api_ioctl.h | 8ce93ec9531c4b7da2d25f2e3957ca13204a3ac1 Mon Jul 28 05:56:33 UTC 2025 Ronak Jain <ronak.jain@amd.com> feat(zynqmp): mark IPI calls secure/non-secure
Use BIT24 of the IPI command header from payload[0] to identify the
caller's security state. If the SMC caller is non-secure, set BIT24
to indicate a non-secure origin.
The mechanism is already present in Versal, Versal NET, and
Versal Gen 2 platforms. Extend the same support to Zynq UltraScale+
MPSoC (ZU+) to align its behavior with newer SoCs.
Change-Id: Ic77926033e76a53c0fa1a9949e6838ec64bd6ae5
Signed-off-by: Ronak Jain <ronak.jain@amd.com>
|
| H A D | zynqmp_pm_svc_main.c | 8ce93ec9531c4b7da2d25f2e3957ca13204a3ac1 Mon Jul 28 05:56:33 UTC 2025 Ronak Jain <ronak.jain@amd.com> feat(zynqmp): mark IPI calls secure/non-secure
Use BIT24 of the IPI command header from payload[0] to identify the
caller's security state. If the SMC caller is non-secure, set BIT24
to indicate a non-secure origin.
The mechanism is already present in Versal, Versal NET, and
Versal Gen 2 platforms. Extend the same support to Zynq UltraScale+
MPSoC (ZU+) to align its behavior with newer SoCs.
Change-Id: Ic77926033e76a53c0fa1a9949e6838ec64bd6ae5
Signed-off-by: Ronak Jain <ronak.jain@amd.com>
|
| H A D | zynqmp_pm_api_sys.c | 8ce93ec9531c4b7da2d25f2e3957ca13204a3ac1 Mon Jul 28 05:56:33 UTC 2025 Ronak Jain <ronak.jain@amd.com> feat(zynqmp): mark IPI calls secure/non-secure
Use BIT24 of the IPI command header from payload[0] to identify the
caller's security state. If the SMC caller is non-secure, set BIT24
to indicate a non-secure origin.
The mechanism is already present in Versal, Versal NET, and
Versal Gen 2 platforms. Extend the same support to Zynq UltraScale+
MPSoC (ZU+) to align its behavior with newer SoCs.
Change-Id: Ic77926033e76a53c0fa1a9949e6838ec64bd6ae5
Signed-off-by: Ronak Jain <ronak.jain@amd.com>
|
| H A D | pm_api_clock.h | 8ce93ec9531c4b7da2d25f2e3957ca13204a3ac1 Mon Jul 28 05:56:33 UTC 2025 Ronak Jain <ronak.jain@amd.com> feat(zynqmp): mark IPI calls secure/non-secure
Use BIT24 of the IPI command header from payload[0] to identify the
caller's security state. If the SMC caller is non-secure, set BIT24
to indicate a non-secure origin.
The mechanism is already present in Versal, Versal NET, and
Versal Gen 2 platforms. Extend the same support to Zynq UltraScale+
MPSoC (ZU+) to align its behavior with newer SoCs.
Change-Id: Ic77926033e76a53c0fa1a9949e6838ec64bd6ae5
Signed-off-by: Ronak Jain <ronak.jain@amd.com>
|
| H A D | pm_client.c | 8ce93ec9531c4b7da2d25f2e3957ca13204a3ac1 Mon Jul 28 05:56:33 UTC 2025 Ronak Jain <ronak.jain@amd.com> feat(zynqmp): mark IPI calls secure/non-secure
Use BIT24 of the IPI command header from payload[0] to identify the
caller's security state. If the SMC caller is non-secure, set BIT24
to indicate a non-secure origin.
The mechanism is already present in Versal, Versal NET, and
Versal Gen 2 platforms. Extend the same support to Zynq UltraScale+
MPSoC (ZU+) to align its behavior with newer SoCs.
Change-Id: Ic77926033e76a53c0fa1a9949e6838ec64bd6ae5
Signed-off-by: Ronak Jain <ronak.jain@amd.com>
|
| H A D | pm_api_ioctl.c | 8ce93ec9531c4b7da2d25f2e3957ca13204a3ac1 Mon Jul 28 05:56:33 UTC 2025 Ronak Jain <ronak.jain@amd.com> feat(zynqmp): mark IPI calls secure/non-secure
Use BIT24 of the IPI command header from payload[0] to identify the
caller's security state. If the SMC caller is non-secure, set BIT24
to indicate a non-secure origin.
The mechanism is already present in Versal, Versal NET, and
Versal Gen 2 platforms. Extend the same support to Zynq UltraScale+
MPSoC (ZU+) to align its behavior with newer SoCs.
Change-Id: Ic77926033e76a53c0fa1a9949e6838ec64bd6ae5
Signed-off-by: Ronak Jain <ronak.jain@amd.com>
|
| H A D | pm_api_clock.c | 8ce93ec9531c4b7da2d25f2e3957ca13204a3ac1 Mon Jul 28 05:56:33 UTC 2025 Ronak Jain <ronak.jain@amd.com> feat(zynqmp): mark IPI calls secure/non-secure
Use BIT24 of the IPI command header from payload[0] to identify the
caller's security state. If the SMC caller is non-secure, set BIT24
to indicate a non-secure origin.
The mechanism is already present in Versal, Versal NET, and
Versal Gen 2 platforms. Extend the same support to Zynq UltraScale+
MPSoC (ZU+) to align its behavior with newer SoCs.
Change-Id: Ic77926033e76a53c0fa1a9949e6838ec64bd6ae5
Signed-off-by: Ronak Jain <ronak.jain@amd.com>
|
| /rk3399_ARM-atf/plat/xilinx/zynqmp/ |
| H A D | plat_psci.c | 8ce93ec9531c4b7da2d25f2e3957ca13204a3ac1 Mon Jul 28 05:56:33 UTC 2025 Ronak Jain <ronak.jain@amd.com> feat(zynqmp): mark IPI calls secure/non-secure
Use BIT24 of the IPI command header from payload[0] to identify the
caller's security state. If the SMC caller is non-secure, set BIT24
to indicate a non-secure origin.
The mechanism is already present in Versal, Versal NET, and
Versal Gen 2 platforms. Extend the same support to Zynq UltraScale+
MPSoC (ZU+) to align its behavior with newer SoCs.
Change-Id: Ic77926033e76a53c0fa1a9949e6838ec64bd6ae5
Signed-off-by: Ronak Jain <ronak.jain@amd.com>
|
| /rk3399_ARM-atf/plat/xilinx/zynqmp/aarch64/ |
| H A D | zynqmp_common.c | 8ce93ec9531c4b7da2d25f2e3957ca13204a3ac1 Mon Jul 28 05:56:33 UTC 2025 Ronak Jain <ronak.jain@amd.com> feat(zynqmp): mark IPI calls secure/non-secure
Use BIT24 of the IPI command header from payload[0] to identify the
caller's security state. If the SMC caller is non-secure, set BIT24
to indicate a non-secure origin.
The mechanism is already present in Versal, Versal NET, and
Versal Gen 2 platforms. Extend the same support to Zynq UltraScale+
MPSoC (ZU+) to align its behavior with newer SoCs.
Change-Id: Ic77926033e76a53c0fa1a9949e6838ec64bd6ae5
Signed-off-by: Ronak Jain <ronak.jain@amd.com>
|