Home
last modified time | relevance | path

Searched +full:two +full:- +full:lane (Results 1 – 25 of 325) sorted by relevance

12345678910>>...13

/OK3568_Linux_fs/u-boot/arch/powerpc/cpu/mpc85xx/
H A Dfsl_corenet_serdes.c2 * Copyright 2009-2011 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
20 * The work-arounds for erratum SERDES8 and SERDES-A001 are linked together.
21 * The code is already very complicated as it is, and separating the two
62 unsigned int lpd; /* RCW lane powerdown bit */
96 int serdes_get_lane_idx(int lane) in serdes_get_lane_idx() argument
98 return lanes[lane].idx; in serdes_get_lane_idx()
101 int serdes_get_bank_by_lane(int lane) in serdes_get_bank_by_lane() argument
103 return lanes[lane].bank; in serdes_get_bank_by_lane()
106 int serdes_lane_enabled(int lane) in serdes_lane_enabled() argument
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/media/
H A Dvideo-interfaces.txt4 ---------------
21 #address-cells = <1>;
22 #size-cells = <0>;
37 a common scheme using '#address-cells', '#size-cells' and 'reg' properties is
41 specify #address-cells, #size-cells properties independently for the 'port'
44 Two 'endpoint' nodes are linked with each other through their 'remote-endpoint'
49 between two devices, e.g. there are logic signal inverters on the lines.
53 a device is partitioned into multiple data busses, e.g. 16-bit input port
54 divided into two separate ITU-R BT.656 8-bit busses. In such case bus-width
55 and data-shift properties can be used to assign physical data lines to each
[all …]
H A Dti,omap3isp.txt4 The DT definitions can be found in include/dt-bindings/media/omap3-isp.h.
9 compatible : must contain "ti,omap3-isp"
11 reg : the two registers sets (physical address and length) for the
17 syscon : the phandle and register offset to the Complex I/O or CSI-PHY
19 ti,phy-type : 0 -- OMAP3ISP_PHY_TYPE_COMPLEX_IO (e.g. 3430)
20 1 -- OMAP3ISP_PHY_TYPE_CSIPHY (e.g. 3630)
21 #clock-cells : Must be 1 --- the ISP provides two external clocks,
24 clock bindings in ../clock/clock-bindings.txt.
27 ---------------------
30 video-interfaces.txt in the same directory.
[all …]
/OK3568_Linux_fs/u-boot/board/freescale/t208xrdb/
H A DREADME1 T2080PCIe-RDB is a Freescale Reference Design Board that hosts the T2080 SoC.
2 It can work in two mode: standalone mode and PCIe endpoint mode.
5 ------------------
6 The T2080 QorIQ multicore processor combines four dual-threaded e6500 Power
7 Architecture processor cores with high-performance datapath acceleration
12 - Four dual-threads 64-bit Power architecture e6500 cores, up to 1.8GHz
13 - 2MB L2 cache and 512KB CoreNet platform cache (CPC)
14 - Hierarchical interconnect fabric
15 - One 32-/64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving
16 - Data Path Acceleration Architecture (DPAA) incorporating acceleration
[all …]
/OK3568_Linux_fs/kernel/Documentation/driver-api/nvdimm/
H A Dbtt.rst2 BTT - Block Translation Table
14 using stored energy in capacitors to complete in-flight block writes, or perhaps
15 in firmware. We don't have this luxury with persistent memory - if a write is in
23 the heart of it, is an indirection table that re-maps all the blocks on the
37 next arena). The following depicts the "On-disk" metadata layout::
40 Backing Store +-------> Arena
41 +---------------+ | +------------------+
43 | Arena 0 +---+ | 4K |
44 | 512G | +------------------+
46 +---------------+ | |
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/media/i2c/
H A Dimx219.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Sony 1/4.0-Inch 8Mpixel CMOS Digital Image Sensor
10 - Dave Stevenson <dave.stevenson@raspberrypi.com>
12 description: |-
13 The Sony imx219 is a 1/4.0-inch CMOS active pixel digital image sensor
16 Image data is sent through MIPI CSI-2, which is configured as either 2 or
30 VDIG-supply:
34 VANA-supply:
[all …]
H A Dst,st-mipid02.txt1 STMicroelectronics MIPID02 CSI-2 to PARALLEL bridge
3 MIPID02 has two CSI-2 input ports, only one of those ports can be active at a
4 time. Active port input stream will be de-serialized and its content outputted
6 CSI-2 first input port is a dual lane 800Mbps per lane whereas CSI-2 second
7 input port is a single lane 800Mbps. Both ports support clock and data lane
8 polarity swap. First port also supports data lane swap.
11 YUV420 8-bit, YUV422 8-bit and YUV420 10-bit.
14 - compatible: shall be "st,st-mipid02"
15 - clocks: reference to the xclk input clock.
16 - clock-names: shall be "xclk".
[all …]
H A Dtc358743.txt1 * Toshiba TC358743 HDMI-RX to MIPI CSI2-TX Bridge
3 The Toshiba TC358743 HDMI-RX to MIPI CSI2-TX (H2C) is a bridge that converts
4 a HDMI stream to MIPI CSI-2 TX. It is programmable through I2C.
8 - compatible: value should be "toshiba,tc358743"
9 - clocks, clock-names: should contain a phandle link to the reference clock
14 - reset-gpios: gpio phandle GPIO connected to the reset pin
15 - interrupts: GPIO connected to the interrupt pin
16 - data-lanes: should be <1 2 3 4> for four-lane operation,
17 or <1 2> for two-lane operation
18 - clock-lanes: should be <0>
[all …]
H A Dadv748x.txt4 HDMI receiver. They can output CSI-2 on two independent outputs TXA and TXB
9 - compatible: Must contain one of the following
10 - "adi,adv7481" for the ADV7481
11 - "adi,adv7482" for the ADV7482
13 - reg: I2C slave addresses
14 The ADV748x has up to twelve 256-byte maps that can be accessed via the
21 - interrupt-names: Should specify the interrupts as "intrq1", "intrq2" and/or
24 - interrupts: Specify the interrupt lines for the ADV748x
25 - reg-names : Names of maps with programmable addresses.
26 It shall contain all maps needing a non-default address.
[all …]
H A Drk628.txt1 * RK628 HDMI-RX to MIPI CSI2-TX Bridge
3 The RK628 HDMI-RX to MIPI CSI2-TX (H2C) is a bridge that converts
4 a HDMI stream to MIPI CSI-2 TX. It is programmable through I2C.
7 - compatible: value should be "rockchip,rk628-csi-v4l2"
8 - reg: I2C device address
11 - reset-gpios: gpio phandle GPIO connected to the reset pin
12 - enable-gpios: a GPIO spec for the enable pin
13 - plugin-det-gpios: HDMI 5V detect pin
14 - interrupts: GPIO connected to the interrupt pin
15 - data-lanes: should be <1 2 3 4> for four-lane operation,
[all …]
/OK3568_Linux_fs/u-boot/board/freescale/t208xqds/
H A DREADME1 The T2080QDS is a high-performance computing evaluation, development and
5 ------------------
6 The T2080 QorIQ multicore processor combines four dual-threaded e6500 Power
7 Architecture processor cores with high-performance datapath acceleration
12 - Four dual-threads 64-bit Power architecture e6500 cores, up to 1.8GHz
13 - 2MB L2 cache and 512KB CoreNet platform cache (CPC)
14 - Hierarchical interconnect fabric
15 - One 32-/64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving
16 - Data Path Acceleration Architecture (DPAA) incorporating acceleration
17 - 16 SerDes lanes up to 10.3125 GHz
[all …]
H A Deth_t208xqds.c6 * SPDX-License-Identifier: GPL-2.0+
135 struct t208xqds_mdio *priv = bus->priv; in t208xqds_mdio_read()
137 t208xqds_mux_mdio(priv->muxval); in t208xqds_mdio_read()
139 return priv->realbus->read(priv->realbus, addr, devad, regnum); in t208xqds_mdio_read()
145 struct t208xqds_mdio *priv = bus->priv; in t208xqds_mdio_write()
147 t208xqds_mux_mdio(priv->muxval); in t208xqds_mdio_write()
149 return priv->realbus->write(priv->realbus, addr, devad, regnum, value); in t208xqds_mdio_write()
154 struct t208xqds_mdio *priv = bus->priv; in t208xqds_mdio_reset()
156 return priv->realbus->reset(priv->realbus); in t208xqds_mdio_reset()
166 return -1; in t208xqds_mdio_init()
[all …]
/OK3568_Linux_fs/kernel/include/linux/platform_data/media/
H A Domap4iss.h1 /* SPDX-License-Identifier: GPL-2.0 */
15 * struct iss_csiphy_lane: CSI2 lane position and polarity
16 * @pos: position of the lane
17 * @pol: polarity of the lane
28 * struct iss_csiphy_lanes_cfg - CSI2 lane configuration
29 * @data: Configuration of one or two data lanes
30 * @clk: Clock lane configuration
38 * struct iss_csi2_platform_data - CSI2 interface platform data
/OK3568_Linux_fs/kernel/drivers/media/platform/omap3isp/
H A Domap3isp.h1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * TI OMAP3 ISP - Bus Configuration
25 * struct isp_parallel_cfg - Parallel interface configuration
26 * @data_lane_shift: Data lane shifter
27 * 0 - CAMEXT[13:0] -> CAM[13:0]
28 * 2 - CAMEXT[13:2] -> CAM[11:0]
29 * 4 - CAMEXT[13:4] -> CAM[9:0]
30 * 6 - CAMEXT[13:6] -> CAM[7:0]
32 * 0 - Sample on rising edge, 1 - Sample on falling edge
34 * 0 - Active high, 1 - Active low
[all …]
/OK3568_Linux_fs/u-boot/board/freescale/p2041rdb/
H A Deth.c5 * SPDX-License-Identifier: GPL-2.0+
9 * The RGMII PHYs are provided by the two on-board PHY. The SGMII PHYs
10 * are provided by the three on-board PHY or by the standard Freescale
11 * four-port SGMII riser card. We need to change the phy-handle in the
30 * that the mapping must be determined dynamically, or that the lane maps to
67 * ... update the phy-handle property of the Ethernet node to point to the
75 * ports in U-Boot because on previous Ethernet devices (e.g. Gianfar), MACs
93 int lane = serdes_get_first_lane(SGMII_FM1_DTSEC1 + port); in board_ft_fman_fixup_port() local
95 if (lane < 0) in board_ft_fman_fixup_port()
97 slot = lane_to_slot[lane]; in board_ft_fman_fixup_port()
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/i915/display/
H A Dintel_dpio_phy.c2 * Copyright © 2014-2016 Intel Corporation
39 * IOSF-SB port.
41 * Each display PHY is made up of one or two channels. Each channel
42 * houses a common lane part which contains the PLL and other common
43 * logic. CH0 common lane also contains the IOSF-SB logic for the
52 * Eeach channel also has two splines (also called data lanes), and
53 * each spline is made up of one Physical Access Coding Sub-Layer
54 * (PCS) block and two TX lanes. So each channel has two PCS blocks
58 * Additionally the PHY also contains an AUX lane with AUX blocks
64 * Generally on VLV/CHV the common lane corresponds to the pipe and
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/dts/
H A Darmada-8040-mcbin.dts4 * SPDX-License-Identifier: GPL-2.0
8 #include "armada-8040.dtsi" /* include SoC device tree */
11 model = "MACCHIATOBin-8040";
12 compatible = "marvell,armada8040-mcbin",
16 stdout-path = "serial0:115200n8";
33 simple-bus {
34 compatible = "simple-bus";
35 #address-cells = <1>;
36 #size-cells = <0>;
38 reg_usb3h0_vbus: usb3-vbus0 {
[all …]
H A Darmada-xp-mv78460.dtsi6 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
8 * This file is dual-licensed: you can use it either under the terms
50 #include "armada-xp.dtsi"
54 compatible = "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp";
64 #address-cells = <1>;
65 #size-cells = <0>;
66 enable-method = "marvell,armada-xp-smp";
70 compatible = "marvell,sheeva-v7";
73 clock-latency = <1000000>;
78 compatible = "marvell,sheeva-v7";
[all …]
/OK3568_Linux_fs/kernel/arch/arm/boot/dts/
H A Darmada-xp-mv78460.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
13 #include "armada-xp.dtsi"
17 compatible = "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp";
27 #address-cells = <1>;
28 #size-cells = <0>;
29 enable-method = "marvell,armada-xp-smp";
33 compatible = "marvell,sheeva-v7";
36 clock-latency = <1000000>;
41 compatible = "marvell,sheeva-v7";
[all …]
/OK3568_Linux_fs/u-boot/board/freescale/ls1043aqds/
H A Deth.c4 * SPDX-License-Identifier: GPL-2.0+
96 struct ls1043aqds_mdio *priv = bus->priv; in ls1043aqds_mdio_read()
98 ls1043aqds_mux_mdio(priv->muxval); in ls1043aqds_mdio_read()
100 return priv->realbus->read(priv->realbus, addr, devad, regnum); in ls1043aqds_mdio_read()
106 struct ls1043aqds_mdio *priv = bus->priv; in ls1043aqds_mdio_write()
108 ls1043aqds_mux_mdio(priv->muxval); in ls1043aqds_mdio_write()
110 return priv->realbus->write(priv->realbus, addr, devad, in ls1043aqds_mdio_write()
116 struct ls1043aqds_mdio *priv = bus->priv; in ls1043aqds_mdio_reset()
118 return priv->realbus->reset(priv->realbus); in ls1043aqds_mdio_reset()
128 return -1; in ls1043aqds_mdio_init()
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/phy/
H A Dti,phy-j721e-wiz.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
4 ---
5 $id: "http://devicetree.org/schemas/phy/ti,phy-j721e-wiz.yaml#"
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
11 - Kishon Vijay Abraham I <kishon@ti.com>
16 - ti,j721e-wiz-16g
17 - ti,j721e-wiz-10g
19 power-domains:
24 description: clock-specifier to represent input to the WIZ
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/pci/
H A Dti-pci.txt4 - compatible: Should be "ti,dra7-pcie" for RC (deprecated)
5 Should be "ti,dra7-pcie-ep" for EP (deprecated)
6 Should be "ti,dra746-pcie-rc" for dra74x/dra76 in RC mode
7 Should be "ti,dra746-pcie-ep" for dra74x/dra76 in EP mode
8 Should be "ti,dra726-pcie-rc" for dra72x in RC mode
9 Should be "ti,dra726-pcie-ep" for dra72x in EP mode
10 - phys : list of PHY specifiers (used by generic PHY framework)
11 - phy-names : must be "pcie-phy0", "pcie-phy1", "pcie-phyN".. based on the
13 - ti,hwmods : Name of the hwmod associated to the pcie, "pcie<X>",
15 - num-lanes as specified in ../designware-pcie.txt
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/cpu/armv8/fsl-layerscape/doc/
H A DREADME.soc11 ---------
12 The LS1043A integrated multicore processor combines four ARM Cortex-A53
18 - Four 64-bit ARM Cortex-A53 CPUs
19 - 1 MB unified L2 Cache
20 - One 32-bit DDR3L/DDR4 SDRAM memory controllers with ECC and interleaving
22 - Data Path Acceleration Architecture (DPAA) incorporating acceleration the
24 - Packet parsing, classification, and distribution (FMan)
25 - Queue management for scheduling, packet sequencing, and congestion
27 - Hardware buffer management for buffer allocation and de-allocation (BMan)
28 - Cryptography acceleration (SEC)
[all …]
/OK3568_Linux_fs/u-boot/board/freescale/ls1046aqds/
H A Deth.c4 * SPDX-License-Identifier: GPL-2.0+
92 struct ls1046aqds_mdio *priv = bus->priv; in ls1046aqds_mdio_read()
94 ls1046aqds_mux_mdio(priv->muxval); in ls1046aqds_mdio_read()
96 return priv->realbus->read(priv->realbus, addr, devad, regnum); in ls1046aqds_mdio_read()
102 struct ls1046aqds_mdio *priv = bus->priv; in ls1046aqds_mdio_write()
104 ls1046aqds_mux_mdio(priv->muxval); in ls1046aqds_mdio_write()
106 return priv->realbus->write(priv->realbus, addr, devad, in ls1046aqds_mdio_write()
112 struct ls1046aqds_mdio *priv = bus->priv; in ls1046aqds_mdio_reset()
114 return priv->realbus->reset(priv->realbus); in ls1046aqds_mdio_reset()
124 return -1; in ls1046aqds_mdio_init()
[all …]
/OK3568_Linux_fs/u-boot/board/freescale/t1040qds/
H A Deth.c4 * SPDX-License-Identifier: GPL-2.0+
8 * The RGMII PHYs are provided by the two on-board PHY connected to
9 * dTSEC instances 4 and 5. The SGMII PHYs are provided by one on-board
10 * PHY or by the standard four-port SGMII riser card (VSC).
29 /* - In T1040 there are only 8 SERDES lanes, spread across 2 SERDES banks.
30 * Bank 1 -> Lanes A, B, C, D
31 * Bank 2 -> Lanes E, F, G, H
35 * means that the mapping must be determined dynamically, or that the lane
121 struct t1040_qds_mdio *priv = bus->priv; in t1040_qds_mdio_read()
123 t1040_qds_mux_mdio(priv->muxval); in t1040_qds_mdio_read()
[all …]

12345678910>>...13