4  * SPDX-License-Identifier:	GPL-2.0+
92 	struct ls1046aqds_mdio *priv = bus->priv;  in ls1046aqds_mdio_read()
94 	ls1046aqds_mux_mdio(priv->muxval);  in ls1046aqds_mdio_read()
96 	return priv->realbus->read(priv->realbus, addr, devad, regnum);  in ls1046aqds_mdio_read()
102 	struct ls1046aqds_mdio *priv = bus->priv;  in ls1046aqds_mdio_write()
104 	ls1046aqds_mux_mdio(priv->muxval);  in ls1046aqds_mdio_write()
106 	return priv->realbus->write(priv->realbus, addr, devad,  in ls1046aqds_mdio_write()
112 	struct ls1046aqds_mdio *priv = bus->priv;  in ls1046aqds_mdio_reset()
114 	return priv->realbus->reset(priv->realbus);  in ls1046aqds_mdio_reset()
124 		return -1;  in ls1046aqds_mdio_init()
131 		return -1;  in ls1046aqds_mdio_init()
134 	bus->read = ls1046aqds_mdio_read;  in ls1046aqds_mdio_init()
135 	bus->write = ls1046aqds_mdio_write;  in ls1046aqds_mdio_init()
136 	bus->reset = ls1046aqds_mdio_reset;  in ls1046aqds_mdio_init()
137 	sprintf(bus->name, ls1046aqds_mdio_name_for_muxval(muxval));  in ls1046aqds_mdio_init()
139 	pmdio->realbus = miiphy_get_dev_by_name(realbusname);  in ls1046aqds_mdio_init()
141 	if (!pmdio->realbus) {  in ls1046aqds_mdio_init()
145 		return -1;  in ls1046aqds_mdio_init()
148 	pmdio->muxval = muxval;  in ls1046aqds_mdio_init()
149 	bus->priv = pmdio;  in ls1046aqds_mdio_init()
186 		fdt_delprop(fdt, offset, "phy-handle");  in board_ft_fman_fixup_port()
187 		fdt_setprop(fdt, offset, "fixed-link", &f_link, sizeof(f_link));  in board_ft_fman_fixup_port()
188 		fdt_setprop_string(fdt, offset, "phy-connection-type",  in board_ft_fman_fixup_port()
189 				   "sgmii-2500");  in board_ft_fman_fixup_port()
207 		fdt_delprop(fdt, offset, "phy-connection-type");  in board_ft_fman_fixup_port()
208 		fdt_setprop_string(fdt, offset, "phy-connection-type",  in board_ft_fman_fixup_port()
219 		fdt_delprop(fdt, offset, "phy-handle");  in board_ft_fman_fixup_port()
220 		fdt_setprop(fdt, offset, "fixed-link", &f_link, sizeof(f_link));  in board_ft_fman_fixup_port()
221 		fdt_setprop_string(fdt, offset, "phy-connection-type", "xgmii");  in board_ft_fman_fixup_port()
256 	int i, idx, lane, slot, interface;  in board_eth_init()  local
262 	srds_s1 = in_be32(&gur->rcwsr[4]) &  in board_eth_init()
266 	srds_s2 = in_be32(&gur->rcwsr[4]) &  in board_eth_init()
282 	/* Register the muxing front-ends to the MDIO buses */  in board_eth_init()
289 	/* Set the two on-board RGMII PHY address */  in board_eth_init()
309 		/* QSGMII on lane B, MAC 6/5/10/1 */  in board_eth_init()
340 		idx = i - FM1_DTSEC1;  in board_eth_init()
347 					/* route lane 2 to slot1 so to have  in board_eth_init()
355 				lane = serdes_get_first_lane(FSL_SRDS_1,  in board_eth_init()
358 				/* clear the bit 7 to route lane B on slot2. */  in board_eth_init()
362 				lane = serdes_get_first_lane(FSL_SRDS_1,  in board_eth_init()
364 				lane_to_slot[lane] = 2;  in board_eth_init()
368 				lane = 5;  in board_eth_init()
370 			if (lane < 0)  in board_eth_init()
373 			slot = lane_to_slot[lane];  in board_eth_init()
376 			if (QIXIS_READ(present2) & (1 << (slot - 1)))  in board_eth_init()