xref: /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/media/i2c/adv748x.txt (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun* Analog Devices ADV748X video decoder with HDMI receiver
2*4882a593Smuzhiyun
3*4882a593SmuzhiyunThe ADV7481 and ADV7482 are multi format video decoders with an integrated
4*4882a593SmuzhiyunHDMI receiver. They can output CSI-2 on two independent outputs TXA and TXB
5*4882a593Smuzhiyunfrom three input sources HDMI, analog and TTL.
6*4882a593Smuzhiyun
7*4882a593SmuzhiyunRequired Properties:
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun  - compatible: Must contain one of the following
10*4882a593Smuzhiyun    - "adi,adv7481" for the ADV7481
11*4882a593Smuzhiyun    - "adi,adv7482" for the ADV7482
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun  - reg: I2C slave addresses
14*4882a593Smuzhiyun    The ADV748x has up to twelve 256-byte maps that can be accessed via the
15*4882a593Smuzhiyun    main I2C ports. Each map has it own I2C address and acts as a standard
16*4882a593Smuzhiyun    slave device on the I2C bus. The main address is mandatory, others are
17*4882a593Smuzhiyun    optional and remain at default values if not specified.
18*4882a593Smuzhiyun
19*4882a593SmuzhiyunOptional Properties:
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun  - interrupt-names: Should specify the interrupts as "intrq1", "intrq2" and/or
22*4882a593Smuzhiyun		     "intrq3". All interrupts are optional. The "intrq3" interrupt
23*4882a593Smuzhiyun		     is only available on the adv7481
24*4882a593Smuzhiyun  - interrupts: Specify the interrupt lines for the ADV748x
25*4882a593Smuzhiyun  - reg-names : Names of maps with programmable addresses.
26*4882a593Smuzhiyun		It shall contain all maps needing a non-default address.
27*4882a593Smuzhiyun		Possible map names are:
28*4882a593Smuzhiyun		  "main", "dpll", "cp", "hdmi", "edid", "repeater",
29*4882a593Smuzhiyun		  "infoframe", "cbus", "cec", "sdp", "txa", "txb"
30*4882a593Smuzhiyun
31*4882a593SmuzhiyunThe device node must contain one 'port' child node per device input and output
32*4882a593Smuzhiyunport, in accordance with the video interface bindings defined in
33*4882a593SmuzhiyunDocumentation/devicetree/bindings/media/video-interfaces.txt. The port nodes
34*4882a593Smuzhiyunare numbered as follows.
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun	  Name		Type		Port
37*4882a593Smuzhiyun	---------------------------------------
38*4882a593Smuzhiyun	  AIN0		sink		0
39*4882a593Smuzhiyun	  AIN1		sink		1
40*4882a593Smuzhiyun	  AIN2		sink		2
41*4882a593Smuzhiyun	  AIN3		sink		3
42*4882a593Smuzhiyun	  AIN4		sink		4
43*4882a593Smuzhiyun	  AIN5		sink		5
44*4882a593Smuzhiyun	  AIN6		sink		6
45*4882a593Smuzhiyun	  AIN7		sink		7
46*4882a593Smuzhiyun	  HDMI		sink		8
47*4882a593Smuzhiyun	  TTL		sink		9
48*4882a593Smuzhiyun	  TXA		source		10
49*4882a593Smuzhiyun	  TXB		source		11
50*4882a593Smuzhiyun
51*4882a593SmuzhiyunThe digital output port nodes, when present, shall contain at least one
52*4882a593Smuzhiyunendpoint. Each of those endpoints shall contain the data-lanes property as
53*4882a593Smuzhiyundescribed in video-interfaces.txt.
54*4882a593Smuzhiyun
55*4882a593SmuzhiyunRequired source endpoint properties:
56*4882a593Smuzhiyun  - data-lanes: an array of physical data lane indexes
57*4882a593Smuzhiyun    The accepted value(s) for this property depends on which of the two
58*4882a593Smuzhiyun    sources are described. For TXA 1, 2 or 4 data lanes can be described
59*4882a593Smuzhiyun    while for TXB only 1 data lane is valid. See video-interfaces.txt
60*4882a593Smuzhiyun    for detailed description.
61*4882a593Smuzhiyun
62*4882a593SmuzhiyunPorts are optional if they are not connected to anything at the hardware level.
63*4882a593Smuzhiyun
64*4882a593SmuzhiyunExample:
65*4882a593Smuzhiyun
66*4882a593Smuzhiyun	video-receiver@70 {
67*4882a593Smuzhiyun		compatible = "adi,adv7482";
68*4882a593Smuzhiyun		reg = <0x70 0x71 0x72 0x73 0x74 0x75
69*4882a593Smuzhiyun		       0x60 0x61 0x62 0x63 0x64 0x65>;
70*4882a593Smuzhiyun		reg-names = "main", "dpll", "cp", "hdmi", "edid", "repeater",
71*4882a593Smuzhiyun			    "infoframe", "cbus", "cec", "sdp", "txa", "txb";
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun		#address-cells = <1>;
74*4882a593Smuzhiyun		#size-cells = <0>;
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun		interrupt-parent = <&gpio6>;
77*4882a593Smuzhiyun		interrupt-names = "intrq1", "intrq2";
78*4882a593Smuzhiyun		interrupts = <30 IRQ_TYPE_LEVEL_LOW>,
79*4882a593Smuzhiyun			     <31 IRQ_TYPE_LEVEL_LOW>;
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun		port@7 {
82*4882a593Smuzhiyun			reg = <7>;
83*4882a593Smuzhiyun
84*4882a593Smuzhiyun			adv7482_ain7: endpoint {
85*4882a593Smuzhiyun				remote-endpoint = <&cvbs_in>;
86*4882a593Smuzhiyun			};
87*4882a593Smuzhiyun		};
88*4882a593Smuzhiyun
89*4882a593Smuzhiyun		port@8 {
90*4882a593Smuzhiyun			reg = <8>;
91*4882a593Smuzhiyun
92*4882a593Smuzhiyun			adv7482_hdmi: endpoint {
93*4882a593Smuzhiyun				remote-endpoint = <&hdmi_in>;
94*4882a593Smuzhiyun			};
95*4882a593Smuzhiyun		};
96*4882a593Smuzhiyun
97*4882a593Smuzhiyun		port@a {
98*4882a593Smuzhiyun			reg = <10>;
99*4882a593Smuzhiyun
100*4882a593Smuzhiyun			adv7482_txa: endpoint {
101*4882a593Smuzhiyun				clock-lanes = <0>;
102*4882a593Smuzhiyun				data-lanes = <1 2 3 4>;
103*4882a593Smuzhiyun				remote-endpoint = <&csi40_in>;
104*4882a593Smuzhiyun			};
105*4882a593Smuzhiyun		};
106*4882a593Smuzhiyun
107*4882a593Smuzhiyun		port@b {
108*4882a593Smuzhiyun			reg = <11>;
109*4882a593Smuzhiyun
110*4882a593Smuzhiyun			adv7482_txb: endpoint {
111*4882a593Smuzhiyun				clock-lanes = <0>;
112*4882a593Smuzhiyun				data-lanes = <1>;
113*4882a593Smuzhiyun				remote-endpoint = <&csi20_in>;
114*4882a593Smuzhiyun			};
115*4882a593Smuzhiyun		};
116*4882a593Smuzhiyun	};
117