4  * SPDX-License-Identifier:	GPL-2.0+
8  * The RGMII PHYs are provided by the two on-board PHY connected to
9  * dTSEC instances 4 and 5. The SGMII PHYs are provided by one on-board
10  * PHY or by the standard four-port SGMII riser card (VSC).
29  /* - In T1040 there are only 8 SERDES lanes, spread across 2 SERDES banks.
30  *   Bank 1 -> Lanes A, B, C, D
31  *   Bank 2 -> Lanes E, F, G, H
35   * means that the mapping must be determined dynamically, or that the lane
121 	struct t1040_qds_mdio *priv = bus->priv;  in t1040_qds_mdio_read()
123 	t1040_qds_mux_mdio(priv->muxval);  in t1040_qds_mdio_read()
125 	return priv->realbus->read(priv->realbus, addr, devad, regnum);  in t1040_qds_mdio_read()
131 	struct t1040_qds_mdio *priv = bus->priv;  in t1040_qds_mdio_write()
133 	t1040_qds_mux_mdio(priv->muxval);  in t1040_qds_mdio_write()
135 	return priv->realbus->write(priv->realbus, addr, devad, regnum, value);  in t1040_qds_mdio_write()
140 	struct t1040_qds_mdio *priv = bus->priv;  in t1040_qds_mdio_reset()
142 	return priv->realbus->reset(priv->realbus);  in t1040_qds_mdio_reset()
152 		return -1;  in t1040_qds_mdio_init()
159 		return -1;  in t1040_qds_mdio_init()
162 	bus->read = t1040_qds_mdio_read;  in t1040_qds_mdio_init()
163 	bus->write = t1040_qds_mdio_write;  in t1040_qds_mdio_init()
164 	bus->reset = t1040_qds_mdio_reset;  in t1040_qds_mdio_init()
165 	strcpy(bus->name, t1040_qds_mdio_name_for_muxval(muxval));  in t1040_qds_mdio_init()
167 	pmdio->realbus = miiphy_get_dev_by_name(realbusname);  in t1040_qds_mdio_init()
169 	if (!pmdio->realbus) {  in t1040_qds_mdio_init()
173 		return -1;  in t1040_qds_mdio_init()
176 	pmdio->muxval = muxval;  in t1040_qds_mdio_init()
177 	bus->priv = pmdio;  in t1040_qds_mdio_init()
190 	int serdes1_prtcl = (in_be32(&gur->rcwsr[4]) &  in initialize_lane_to_slot()
274  * ... update the phy-handle property of the Ethernet node to point to the
282  * ports in U-Boot because on previous Ethernet devices (e.g. Gianfar), MACs
300 		int lane = serdes_get_first_lane(FSL_SRDS_1, SGMII_FM1_DTSEC1  in board_ft_fman_fixup_port()  local
303 		if (lane < 0)  in board_ft_fman_fixup_port()
305 		slot = lane_to_slot[lane];  in board_ft_fman_fixup_port()
309 				(fm_info_get_phy_address(port - FM1_DTSEC1)-  in board_ft_fman_fixup_port()
318 	int i, lane, idx;  in fdt_fixup_board_enet()  local
321 		idx = i - FM1_DTSEC1;  in fdt_fixup_board_enet()
324 			lane = serdes_get_first_lane(FSL_SRDS_1,  in fdt_fixup_board_enet()
326 			if (lane < 0)  in fdt_fixup_board_enet()
370 	int lane, idx, slot;  in t1040_handle_phy_interface_sgmii()  local
371 	idx = i - FM1_DTSEC1;  in t1040_handle_phy_interface_sgmii()
372 	lane = serdes_get_first_lane(FSL_SRDS_1,  in t1040_handle_phy_interface_sgmii()
375 	if (lane < 0)  in t1040_handle_phy_interface_sgmii()
377 	slot = lane_to_slot[lane];  in t1040_handle_phy_interface_sgmii()
444 	int lane;  in board_eth_init()  local
466 	/* Register the muxing front-ends to the MDIO buses */  in board_eth_init()
505 		lane = -1;  in board_eth_init()
513 			lane = serdes_get_first_lane(FSL_SRDS_1, QSGMII_SW1_A);  in board_eth_init()
515 			if (lane >= 0) {  in board_eth_init()
521 			lane = serdes_get_first_lane(FSL_SRDS_1,  in board_eth_init()
524 			if (lane < 0)  in board_eth_init()
528 			if (i != 3 || lane_to_slot[lane] == 7)  in board_eth_init()
539 			lane = serdes_get_first_lane(FSL_SRDS_1, QSGMII_SW1_B);  in board_eth_init()
541 			if (lane >= 0) {  in board_eth_init()
543 						i - 4;  in board_eth_init()
547 			lane = serdes_get_first_lane(FSL_SRDS_1,  in board_eth_init()
550 			if (lane >= 0) {  in board_eth_init()
552 						+ i - 3;  in board_eth_init()
569 				out_be32(&scfg->esgmiiselcr,  in board_eth_init()
570 					 in_be32(&scfg->esgmiiselcr) |  in board_eth_init()
577 		if (lane >= 0) {  in board_eth_init()
578 			bus = mii_dev_for_muxval(lane_to_slot[lane]);  in board_eth_init()