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/OK3568_Linux_fs/kernel/drivers/gpu/drm/tegra/
H A Dmipi-phy.c16 int mipi_dphy_timing_get_default(struct mipi_dphy_timing *timing, in mipi_dphy_timing_get_default() argument
19 timing->clkmiss = 0; in mipi_dphy_timing_get_default()
20 timing->clkpost = 70 + 52 * period; in mipi_dphy_timing_get_default()
21 timing->clkpre = 8; in mipi_dphy_timing_get_default()
22 timing->clkprepare = 65; in mipi_dphy_timing_get_default()
23 timing->clksettle = 95; in mipi_dphy_timing_get_default()
24 timing->clktermen = 0; in mipi_dphy_timing_get_default()
25 timing->clktrail = 80; in mipi_dphy_timing_get_default()
26 timing->clkzero = 260; in mipi_dphy_timing_get_default()
27 timing->dtermen = 0; in mipi_dphy_timing_get_default()
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/msm/dsi/phy/
H A Ddsi_phy.c26 static void dsi_dphy_timing_calc_clk_zero(struct msm_dsi_dphy_timing *timing, in dsi_dphy_timing_calc_clk_zero() argument
33 temp = 300 * coeff - ((timing->clk_prepare >> 1) + 1) * 2 * ui; in dsi_dphy_timing_calc_clk_zero()
44 temp = (timing->hs_rqst + timing->clk_prepare + clk_z) & 0x7; in dsi_dphy_timing_calc_clk_zero()
45 timing->clk_zero = clk_z + 8 - temp; in dsi_dphy_timing_calc_clk_zero()
48 int msm_dsi_dphy_timing_calc(struct msm_dsi_dphy_timing *timing, in msm_dsi_dphy_timing_calc() argument
70 timing->clk_prepare = linear_inter(tmax, tmin, pcnt0, 0, true); in msm_dsi_dphy_timing_calc()
74 timing->hs_rqst = temp; in msm_dsi_dphy_timing_calc()
76 timing->hs_rqst = max_t(s32, 0, temp - 2); in msm_dsi_dphy_timing_calc()
79 dsi_dphy_timing_calc_clk_zero(timing, ui, coeff, pcnt2); in msm_dsi_dphy_timing_calc()
84 timing->clk_trail = linear_inter(tmax, tmin, pcnt3, 0, true); in msm_dsi_dphy_timing_calc()
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H A Ddsi_phy_14nm.c14 struct msm_dsi_dphy_timing *timing, in dsi_14nm_dphy_set_timing() argument
19 u32 zero = clk_ln ? timing->clk_zero : timing->hs_zero; in dsi_14nm_dphy_set_timing()
20 u32 prepare = clk_ln ? timing->clk_prepare : timing->hs_prepare; in dsi_14nm_dphy_set_timing()
21 u32 trail = clk_ln ? timing->clk_trail : timing->hs_trail; in dsi_14nm_dphy_set_timing()
22 u32 rqst = clk_ln ? timing->hs_rqst_ckln : timing->hs_rqst; in dsi_14nm_dphy_set_timing()
23 u32 prep_dly = clk_ln ? timing->hs_prep_dly_ckln : timing->hs_prep_dly; in dsi_14nm_dphy_set_timing()
24 u32 halfbyte_en = clk_ln ? timing->hs_halfbyte_en_ckln : in dsi_14nm_dphy_set_timing()
25 timing->hs_halfbyte_en; in dsi_14nm_dphy_set_timing()
28 DSI_14nm_PHY_LN_TIMING_CTRL_4_HS_EXIT(timing->hs_exit)); in dsi_14nm_dphy_set_timing()
42 DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_GO(timing->ta_go) | in dsi_14nm_dphy_set_timing()
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H A Ddsi_phy_20nm.c10 struct msm_dsi_dphy_timing *timing) in dsi_20nm_dphy_set_timing() argument
15 DSI_20nm_PHY_TIMING_CTRL_0_CLK_ZERO(timing->clk_zero)); in dsi_20nm_dphy_set_timing()
17 DSI_20nm_PHY_TIMING_CTRL_1_CLK_TRAIL(timing->clk_trail)); in dsi_20nm_dphy_set_timing()
19 DSI_20nm_PHY_TIMING_CTRL_2_CLK_PREPARE(timing->clk_prepare)); in dsi_20nm_dphy_set_timing()
20 if (timing->clk_zero & BIT(8)) in dsi_20nm_dphy_set_timing()
24 DSI_20nm_PHY_TIMING_CTRL_4_HS_EXIT(timing->hs_exit)); in dsi_20nm_dphy_set_timing()
26 DSI_20nm_PHY_TIMING_CTRL_5_HS_ZERO(timing->hs_zero)); in dsi_20nm_dphy_set_timing()
28 DSI_20nm_PHY_TIMING_CTRL_6_HS_PREPARE(timing->hs_prepare)); in dsi_20nm_dphy_set_timing()
30 DSI_20nm_PHY_TIMING_CTRL_7_HS_TRAIL(timing->hs_trail)); in dsi_20nm_dphy_set_timing()
32 DSI_20nm_PHY_TIMING_CTRL_8_HS_RQST(timing->hs_rqst)); in dsi_20nm_dphy_set_timing()
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H A Ddsi_phy_28nm.c10 struct msm_dsi_dphy_timing *timing) in dsi_28nm_dphy_set_timing() argument
15 DSI_28nm_PHY_TIMING_CTRL_0_CLK_ZERO(timing->clk_zero)); in dsi_28nm_dphy_set_timing()
17 DSI_28nm_PHY_TIMING_CTRL_1_CLK_TRAIL(timing->clk_trail)); in dsi_28nm_dphy_set_timing()
19 DSI_28nm_PHY_TIMING_CTRL_2_CLK_PREPARE(timing->clk_prepare)); in dsi_28nm_dphy_set_timing()
20 if (timing->clk_zero & BIT(8)) in dsi_28nm_dphy_set_timing()
24 DSI_28nm_PHY_TIMING_CTRL_4_HS_EXIT(timing->hs_exit)); in dsi_28nm_dphy_set_timing()
26 DSI_28nm_PHY_TIMING_CTRL_5_HS_ZERO(timing->hs_zero)); in dsi_28nm_dphy_set_timing()
28 DSI_28nm_PHY_TIMING_CTRL_6_HS_PREPARE(timing->hs_prepare)); in dsi_28nm_dphy_set_timing()
30 DSI_28nm_PHY_TIMING_CTRL_7_HS_TRAIL(timing->hs_trail)); in dsi_28nm_dphy_set_timing()
32 DSI_28nm_PHY_TIMING_CTRL_8_HS_RQST(timing->hs_rqst)); in dsi_28nm_dphy_set_timing()
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H A Ddsi_phy_28nm_8960.c12 struct msm_dsi_dphy_timing *timing) in dsi_28nm_dphy_set_timing() argument
17 DSI_28nm_8960_PHY_TIMING_CTRL_0_CLK_ZERO(timing->clk_zero)); in dsi_28nm_dphy_set_timing()
19 DSI_28nm_8960_PHY_TIMING_CTRL_1_CLK_TRAIL(timing->clk_trail)); in dsi_28nm_dphy_set_timing()
21 DSI_28nm_8960_PHY_TIMING_CTRL_2_CLK_PREPARE(timing->clk_prepare)); in dsi_28nm_dphy_set_timing()
24 DSI_28nm_8960_PHY_TIMING_CTRL_4_HS_EXIT(timing->hs_exit)); in dsi_28nm_dphy_set_timing()
26 DSI_28nm_8960_PHY_TIMING_CTRL_5_HS_ZERO(timing->hs_zero)); in dsi_28nm_dphy_set_timing()
28 DSI_28nm_8960_PHY_TIMING_CTRL_6_HS_PREPARE(timing->hs_prepare)); in dsi_28nm_dphy_set_timing()
30 DSI_28nm_8960_PHY_TIMING_CTRL_7_HS_TRAIL(timing->hs_trail)); in dsi_28nm_dphy_set_timing()
32 DSI_28nm_8960_PHY_TIMING_CTRL_8_HS_RQST(timing->hs_rqst)); in dsi_28nm_dphy_set_timing()
34 DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_GO(timing->ta_go) | in dsi_28nm_dphy_set_timing()
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/OK3568_Linux_fs/kernel/drivers/clk/tegra/
H A Dclk-tegra124-emc.c47 * When we change the timing to a timing with a parent that has the same
49 * timing that has a different clock source.
116 struct emc_timing *timing = NULL; in emc_determine_rate() local
132 timing = tegra->timings + i; in emc_determine_rate()
134 if (timing->rate < req->rate && i != t - 1) in emc_determine_rate()
137 if (timing->rate > req->max_rate) { in emc_determine_rate()
143 if (timing->rate < req->min_rate) in emc_determine_rate()
146 req->rate = timing->rate; in emc_determine_rate()
150 if (timing) { in emc_determine_rate()
151 req->rate = timing->rate; in emc_determine_rate()
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/OK3568_Linux_fs/u-boot/drivers/video/tegra124/
H A Ddisplay.c28 static int tegra_dc_calc_refresh(const struct display_timing *timing) in tegra_dc_calc_refresh() argument
31 int pclk = timing->pixelclock.typ; in tegra_dc_calc_refresh()
33 h_total = timing->hactive.typ + timing->hfront_porch.typ + in tegra_dc_calc_refresh()
34 timing->hback_porch.typ + timing->hsync_len.typ; in tegra_dc_calc_refresh()
35 v_total = timing->vactive.typ + timing->vfront_porch.typ + in tegra_dc_calc_refresh()
36 timing->vback_porch.typ + timing->vsync_len.typ; in tegra_dc_calc_refresh()
46 static void print_mode(const struct display_timing *timing) in print_mode() argument
48 int refresh = tegra_dc_calc_refresh(timing); in print_mode()
51 timing->hactive.typ, timing->vactive.typ, refresh / 1000, in print_mode()
52 refresh % 1000, timing->pixelclock.typ); in print_mode()
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/OK3568_Linux_fs/u-boot/drivers/video/
H A Datmel_lcdfb.c33 struct display_timing timing; member
115 static void atmel_fb_init(ulong addr, struct display_timing *timing, int bpix, in atmel_fb_init() argument
135 value = (timing->hactive.typ * timing->vactive.typ * in atmel_fb_init()
141 value = get_lcdc_clk_rate(0) / timing->pixelclock.typ; in atmel_fb_init()
142 if (get_lcdc_clk_rate(0) % timing->pixelclock.typ) in atmel_fb_init()
157 if (!(timing->flags & DISPLAY_FLAGS_HSYNC_HIGH)) in atmel_fb_init()
159 if (!(timing->flags & DISPLAY_FLAGS_VSYNC_HIGH)) in atmel_fb_init()
164 /* Vertical timing */ in atmel_fb_init()
165 value = (timing->vsync_len.typ - 1) << ATMEL_LCDC_VPW_OFFSET; in atmel_fb_init()
166 value |= timing->vback_porch.typ << ATMEL_LCDC_VBP_OFFSET; in atmel_fb_init()
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/OK3568_Linux_fs/kernel/drivers/memory/tegra/
H A Dtegra124-emc.c486 /* Timing change sequence functions */
509 dev_err(emc->dev, "timing update timed out\n"); in emc_seq_update_timing()
547 struct emc_timing *timing = NULL; in tegra_emc_find_timing() local
552 timing = &emc->timings[i]; in tegra_emc_find_timing()
557 if (!timing) { in tegra_emc_find_timing()
558 dev_err(emc->dev, "no timing for rate %lu\n", rate); in tegra_emc_find_timing()
562 return timing; in tegra_emc_find_timing()
568 struct emc_timing *timing = tegra_emc_find_timing(emc, rate); in tegra_emc_prepare_timing_change() local
576 if (!timing) in tegra_emc_prepare_timing_change()
579 if ((last->emc_mode_1 & 0x1) == (timing->emc_mode_1 & 0x1)) in tegra_emc_prepare_timing_change()
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H A Dtegra30-emc.c368 dev_err(emc->dev, "failed to update timing: %d\n", err); in emc_seq_update_timing()
399 struct emc_timing *timing = NULL; in emc_find_timing() local
404 timing = &emc->timings[i]; in emc_find_timing()
409 if (!timing) { in emc_find_timing()
410 dev_err(emc->dev, "no timing for rate %lu\n", rate); in emc_find_timing()
414 return timing; in emc_find_timing()
417 static bool emc_dqs_preset(struct tegra_emc *emc, struct emc_timing *timing, in emc_dqs_preset() argument
423 if (timing->data[71] & EMC_XM2DQSPADCTRL2_VREF_ENABLE) { in emc_dqs_preset()
434 if (timing->data[78] & EMC_XM2DQSPADCTRL3_VREF_ENABLE) { in emc_dqs_preset()
445 if (timing->data[77] & EMC_XM2QUSEPADCTRL_IVREF_ENABLE) { in emc_dqs_preset()
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/OK3568_Linux_fs/kernel/drivers/gpu/drm/nouveau/nvkm/subdev/bios/
H A Dtiming.c26 #include <subdev/bios/timing.h>
33 u32 timing = 0; in nvbios_timingTe() local
37 timing = nvbios_rd32(bios, bit_P.offset + 4); in nvbios_timingTe()
40 timing = nvbios_rd32(bios, bit_P.offset + 8); in nvbios_timingTe()
42 if (timing) { in nvbios_timingTe()
43 *ver = nvbios_rd08(bios, timing + 0); in nvbios_timingTe()
46 *hdr = nvbios_rd08(bios, timing + 1); in nvbios_timingTe()
47 *cnt = nvbios_rd08(bios, timing + 2); in nvbios_timingTe()
48 *len = nvbios_rd08(bios, timing + 3); in nvbios_timingTe()
51 return timing; in nvbios_timingTe()
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/OK3568_Linux_fs/prebuilts/gcc/linux-x86/arm/gcc-arm-10.3-2021.07-x86_64-arm-none-linux-gnueabihf/lib/gcc/arm-none-linux-gnueabihf/10.3.1/plugin/include/
H A Dtimevar.h1 /* Timing variables for measuring compiler performance.
24 /* Timing variables are used to measure elapsed time in various
29 Timing variables are defined using the DEFTIMEVAR macro in
31 to the timing variable in code, and a character string name.
33 Timing variables can be used in two ways:
35 - On the timing stack, using timevar_push and timevar_pop.
36 Timing variables may be pushed onto the stack; elapsed time is
37 attributed to the topmost timing variable on the stack. When
68 /* An enumeration of timing variable identifiers. Constructed from
82 /* A class to hold all state relating to timing. */
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/OK3568_Linux_fs/prebuilts/gcc/linux-x86/aarch64/gcc-arm-10.3-2021.07-x86_64-aarch64-none-linux-gnu/lib/gcc/aarch64-none-linux-gnu/10.3.1/plugin/include/
H A Dtimevar.h1 /* Timing variables for measuring compiler performance.
24 /* Timing variables are used to measure elapsed time in various
29 Timing variables are defined using the DEFTIMEVAR macro in
31 to the timing variable in code, and a character string name.
33 Timing variables can be used in two ways:
35 - On the timing stack, using timevar_push and timevar_pop.
36 Timing variables may be pushed onto the stack; elapsed time is
37 attributed to the topmost timing variable on the stack. When
68 /* An enumeration of timing variable identifiers. Constructed from
82 /* A class to hold all state relating to timing. */
[all …]
/OK3568_Linux_fs/kernel/drivers/video/fbdev/
H A Dgbefb.c37 struct gbe_timing_info timing; member
412 static void gbefb_setup_flatpanel(struct gbe_timing_info *timing) in gbefb_setup_flatpanel() argument
418 (timing->flags & FB_SYNC_HOR_HIGH_ACT) ? 0 : 1); in gbefb_setup_flatpanel()
420 (timing->flags & FB_SYNC_VERT_HIGH_ACT) ? 0 : 1); in gbefb_setup_flatpanel()
428 timing->pll_m = 4; in gbefb_setup_flatpanel()
429 timing->pll_n = 1; in gbefb_setup_flatpanel()
430 timing->pll_p = 0; in gbefb_setup_flatpanel()
457 struct gbe_timing_info *timing) in compute_gbe_timing() argument
468 /* Determine valid resolution and timing in compute_gbe_timing()
504 /* set video timing information */ in compute_gbe_timing()
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/OK3568_Linux_fs/kernel/drivers/devfreq/
H A Drk3399_dmc.c65 struct dram_timing timing; member
241 static int of_get_ddr_timings(struct dram_timing *timing, in of_get_ddr_timings() argument
247 &timing->ddr3_speed_bin); in of_get_ddr_timings()
249 &timing->pd_idle); in of_get_ddr_timings()
251 &timing->sr_idle); in of_get_ddr_timings()
253 &timing->sr_mc_gate_idle); in of_get_ddr_timings()
255 &timing->srpd_lite_idle); in of_get_ddr_timings()
257 &timing->standby_idle); in of_get_ddr_timings()
259 &timing->auto_pd_dis_freq); in of_get_ddr_timings()
261 &timing->dram_dll_dis_freq); in of_get_ddr_timings()
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/OK3568_Linux_fs/kernel/drivers/gpu/drm/msm/disp/dpu1/
H A Ddpu_encoder_phys_vid.c41 struct intf_timing_params *timing) in drm_mode_to_intf_timing_params() argument
43 memset(timing, 0, sizeof(*timing)); in drm_mode_to_intf_timing_params()
70 timing->width = mode->hdisplay; /* active width */ in drm_mode_to_intf_timing_params()
71 timing->height = mode->vdisplay; /* active height */ in drm_mode_to_intf_timing_params()
72 timing->xres = timing->width; in drm_mode_to_intf_timing_params()
73 timing->yres = timing->height; in drm_mode_to_intf_timing_params()
74 timing->h_back_porch = mode->htotal - mode->hsync_end; in drm_mode_to_intf_timing_params()
75 timing->h_front_porch = mode->hsync_start - mode->hdisplay; in drm_mode_to_intf_timing_params()
76 timing->v_back_porch = mode->vtotal - mode->vsync_end; in drm_mode_to_intf_timing_params()
77 timing->v_front_porch = mode->vsync_start - mode->vdisplay; in drm_mode_to_intf_timing_params()
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/OK3568_Linux_fs/u-boot/drivers/ram/
H A Dstm32_sdram.c19 u32 btr1; /* SRAM/NOR-Flash Chip select timing register 1 */
21 u32 btr2; /* SRAM/NOR-Flash Chip select timing register 2 */
23 u32 btr3; /* SRAM/NOR-Flash Chip select timing register 3 */
25 u32 btr4; /* SRAM/NOR-Flash Chip select timing register 4 */
31 u32 pmem; /* Common memory space timing register */
32 u32 patt; /* Attribute memory space timing registers */
38 u32 bwtr1; /* SRAM/NOR-Flash write timing register 1 */
40 u32 bwtr2; /* SRAM/NOR-Flash write timing register 2 */
42 u32 bwtr3; /* SRAM/NOR-Flash write timing register 3 */
44 u32 bwtr4; /* SRAM/NOR-Flash write timing register 4 */
[all …]
/OK3568_Linux_fs/kernel/drivers/video/fbdev/via/
H A Dvia_modesetting.c18 void via_set_primary_timing(const struct via_display_timing *timing) in via_set_primary_timing() argument
22 raw.hor_total = timing->hor_total / 8 - 5; in via_set_primary_timing()
23 raw.hor_addr = timing->hor_addr / 8 - 1; in via_set_primary_timing()
24 raw.hor_blank_start = timing->hor_blank_start / 8 - 1; in via_set_primary_timing()
25 raw.hor_blank_end = timing->hor_blank_end / 8 - 1; in via_set_primary_timing()
26 raw.hor_sync_start = timing->hor_sync_start / 8; in via_set_primary_timing()
27 raw.hor_sync_end = timing->hor_sync_end / 8; in via_set_primary_timing()
28 raw.ver_total = timing->ver_total - 2; in via_set_primary_timing()
29 raw.ver_addr = timing->ver_addr - 1; in via_set_primary_timing()
30 raw.ver_blank_start = timing->ver_blank_start - 1; in via_set_primary_timing()
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/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/display/dc/dce110/
H A Ddce110_timing_generator_v.c45 * DCE11 Timing Generator Implementation
244 const struct dc_crtc_timing *timing) in dce110_timing_generator_v_program_blanking() argument
246 uint32_t vsync_offset = timing->v_border_bottom + in dce110_timing_generator_v_program_blanking()
247 timing->v_front_porch; in dce110_timing_generator_v_program_blanking()
248 uint32_t v_sync_start = timing->v_addressable + vsync_offset; in dce110_timing_generator_v_program_blanking()
250 uint32_t hsync_offset = timing->h_border_right + in dce110_timing_generator_v_program_blanking()
251 timing->h_front_porch; in dce110_timing_generator_v_program_blanking()
252 uint32_t h_sync_start = timing->h_addressable + hsync_offset; in dce110_timing_generator_v_program_blanking()
263 timing->h_total - 1, in dce110_timing_generator_v_program_blanking()
272 timing->v_total - 1, in dce110_timing_generator_v_program_blanking()
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/nouveau/nvkm/subdev/fb/
H A Dramnv50.c34 #include <subdev/bios/timing.h>
73 nv50_ram_timing_calc(struct nv50_ram *ram, u32 *timing) in nv50_ram_timing_calc() argument
98 timing[6] = (0x2d + T(CL) - T(CWL) + in nv50_ram_timing_calc()
104 timing[6] = (0x2b + T(CL) - T(CWL)) << 16 | in nv50_ram_timing_calc()
109 timing[0] = (T(RP) << 24 | T(RAS) << 16 | T(RFC) << 8 | T(RC)); in nv50_ram_timing_calc()
110 timing[1] = (T(WR) + 1 + T(CWL)) << 24 | in nv50_ram_timing_calc()
114 timing[2] = (T(CWL) - 1) << 24 | in nv50_ram_timing_calc()
118 timing[3] = (unkt3b - 2 + T(CL)) << 24 | in nv50_ram_timing_calc()
122 timing[4] = (cur4 & 0xffff0000) | in nv50_ram_timing_calc()
125 timing[5] = T(RFC) << 24 | in nv50_ram_timing_calc()
[all …]
/OK3568_Linux_fs/kernel/drivers/media/rc/img-ir/
H A Dimg-ir-hw.h22 /* Timing information */
53 * struct img_ir_timing_range - range of timing values
54 * @min: Minimum timing value
55 * @max: Maximum timing value (if < @min, this will be set to @min during
65 * struct img_ir_symbol_timing - timing data for a symbol
66 * @pulse: Timing range for the length of the pulse in this symbol
67 * @space: Timing range for the length of the space in this symbol
75 * struct img_ir_free_timing - timing data for free time symbol
88 * struct img_ir_timings - Timing values.
89 * @ldr: Leader symbol timing data
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/sti/
H A Dsti_awg_utils.c122 struct awg_timing *timing) in awg_generate_line_signal() argument
127 if (timing->trailing_pixels > 0) { in awg_generate_line_signal()
129 val = timing->blanking_level; in awg_generate_line_signal()
132 val = timing->trailing_pixels - 1 + AWG_DELAY; in awg_generate_line_signal()
137 val = timing->blanking_level; in awg_generate_line_signal()
138 ret |= awg_generate_instr((timing->trailing_pixels > 0) ? SET : RPLSET, in awg_generate_line_signal()
141 if (timing->blanking_pixels > 0) { in awg_generate_line_signal()
143 val = timing->active_pixels - 1; in awg_generate_line_signal()
147 val = timing->blanking_level; in awg_generate_line_signal()
156 struct awg_timing *timing) in sti_awg_generate_code_data_enable_mode() argument
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/display/dc/dsc/
H A Ddc_dsc.c41 const struct dc_crtc_timing *timing) in dc_dsc_bandwidth_in_kbps_from_timing() argument
46 if (timing->flags.DSC) { in dc_dsc_bandwidth_in_kbps_from_timing()
47 kbps = (timing->pix_clk_100hz * timing->dsc_cfg.bits_per_pixel); in dc_dsc_bandwidth_in_kbps_from_timing()
52 switch (timing->display_color_depth) { in dc_dsc_bandwidth_in_kbps_from_timing()
77 kbps = timing->pix_clk_100hz / 10; in dc_dsc_bandwidth_in_kbps_from_timing()
80 if (timing->flags.Y_ONLY != 1) { in dc_dsc_bandwidth_in_kbps_from_timing()
83 if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420) in dc_dsc_bandwidth_in_kbps_from_timing()
85 else if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR422) in dc_dsc_bandwidth_in_kbps_from_timing()
314 /* Get DSC bandwidth range based on [min_bpp, max_bpp] target bitrate range, and timing's pixel clo…
321 const struct dc_crtc_timing *timing, in get_dsc_bandwidth_range() argument
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/OK3568_Linux_fs/u-boot/drivers/video/drm/
H A Dinno_mipi_phy.c276 static void mipi_dphy_timing_get_default(struct mipi_dphy_timing *timing, in mipi_dphy_timing_get_default() argument
279 /* Global Operation Timing Parameters */ in mipi_dphy_timing_get_default()
280 timing->clkmiss = 0; in mipi_dphy_timing_get_default()
281 timing->clkpost = 70 + 52 * period; in mipi_dphy_timing_get_default()
282 timing->clkpre = 8 * period; in mipi_dphy_timing_get_default()
283 timing->clkprepare = 65; in mipi_dphy_timing_get_default()
284 timing->clksettle = 95; in mipi_dphy_timing_get_default()
285 timing->clktermen = 0; in mipi_dphy_timing_get_default()
286 timing->clktrail = 80; in mipi_dphy_timing_get_default()
287 timing->clkzero = 260; in mipi_dphy_timing_get_default()
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