xref: /OK3568_Linux_fs/kernel/drivers/media/rc/img-ir/img-ir-hw.h (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * ImgTec IR Hardware Decoder found in PowerDown Controller.
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * Copyright 2010-2014 Imagination Technologies Ltd.
6*4882a593Smuzhiyun  */
7*4882a593Smuzhiyun 
8*4882a593Smuzhiyun #ifndef _IMG_IR_HW_H_
9*4882a593Smuzhiyun #define _IMG_IR_HW_H_
10*4882a593Smuzhiyun 
11*4882a593Smuzhiyun #include <linux/kernel.h>
12*4882a593Smuzhiyun #include <media/rc-core.h>
13*4882a593Smuzhiyun 
14*4882a593Smuzhiyun /* constants */
15*4882a593Smuzhiyun 
16*4882a593Smuzhiyun #define IMG_IR_CODETYPE_PULSELEN	0x0	/* Sony */
17*4882a593Smuzhiyun #define IMG_IR_CODETYPE_PULSEDIST	0x1	/* NEC, Toshiba, Micom, Sharp */
18*4882a593Smuzhiyun #define IMG_IR_CODETYPE_BIPHASE		0x2	/* RC-5/6 */
19*4882a593Smuzhiyun #define IMG_IR_CODETYPE_2BITPULSEPOS	0x3	/* RC-MM */
20*4882a593Smuzhiyun 
21*4882a593Smuzhiyun 
22*4882a593Smuzhiyun /* Timing information */
23*4882a593Smuzhiyun 
24*4882a593Smuzhiyun /**
25*4882a593Smuzhiyun  * struct img_ir_control - Decoder control settings
26*4882a593Smuzhiyun  * @decoden:	Primary decoder enable
27*4882a593Smuzhiyun  * @code_type:	Decode type (see IMG_IR_CODETYPE_*)
28*4882a593Smuzhiyun  * @hdrtog:	Detect header toggle symbol after leader symbol
29*4882a593Smuzhiyun  * @ldrdec:	Don't discard leader if maximum width reached
30*4882a593Smuzhiyun  * @decodinpol:	Decoder input polarity (1=active high)
31*4882a593Smuzhiyun  * @bitorien:	Bit orientation (1=MSB first)
32*4882a593Smuzhiyun  * @d1validsel:	Decoder 2 takes over if it detects valid data
33*4882a593Smuzhiyun  * @bitinv:	Bit inversion switch (1=don't invert)
34*4882a593Smuzhiyun  * @decodend2:	Secondary decoder enable (no leader symbol)
35*4882a593Smuzhiyun  * @bitoriend2:	Bit orientation (1=MSB first)
36*4882a593Smuzhiyun  * @bitinvd2:	Secondary decoder bit inversion switch (1=don't invert)
37*4882a593Smuzhiyun  */
38*4882a593Smuzhiyun struct img_ir_control {
39*4882a593Smuzhiyun 	unsigned decoden:1;
40*4882a593Smuzhiyun 	unsigned code_type:2;
41*4882a593Smuzhiyun 	unsigned hdrtog:1;
42*4882a593Smuzhiyun 	unsigned ldrdec:1;
43*4882a593Smuzhiyun 	unsigned decodinpol:1;
44*4882a593Smuzhiyun 	unsigned bitorien:1;
45*4882a593Smuzhiyun 	unsigned d1validsel:1;
46*4882a593Smuzhiyun 	unsigned bitinv:1;
47*4882a593Smuzhiyun 	unsigned decodend2:1;
48*4882a593Smuzhiyun 	unsigned bitoriend2:1;
49*4882a593Smuzhiyun 	unsigned bitinvd2:1;
50*4882a593Smuzhiyun };
51*4882a593Smuzhiyun 
52*4882a593Smuzhiyun /**
53*4882a593Smuzhiyun  * struct img_ir_timing_range - range of timing values
54*4882a593Smuzhiyun  * @min:	Minimum timing value
55*4882a593Smuzhiyun  * @max:	Maximum timing value (if < @min, this will be set to @min during
56*4882a593Smuzhiyun  *		preprocessing step, so it is normally not explicitly initialised
57*4882a593Smuzhiyun  *		and is taken care of by the tolerance)
58*4882a593Smuzhiyun  */
59*4882a593Smuzhiyun struct img_ir_timing_range {
60*4882a593Smuzhiyun 	u16 min;
61*4882a593Smuzhiyun 	u16 max;
62*4882a593Smuzhiyun };
63*4882a593Smuzhiyun 
64*4882a593Smuzhiyun /**
65*4882a593Smuzhiyun  * struct img_ir_symbol_timing - timing data for a symbol
66*4882a593Smuzhiyun  * @pulse:	Timing range for the length of the pulse in this symbol
67*4882a593Smuzhiyun  * @space:	Timing range for the length of the space in this symbol
68*4882a593Smuzhiyun  */
69*4882a593Smuzhiyun struct img_ir_symbol_timing {
70*4882a593Smuzhiyun 	struct img_ir_timing_range pulse;
71*4882a593Smuzhiyun 	struct img_ir_timing_range space;
72*4882a593Smuzhiyun };
73*4882a593Smuzhiyun 
74*4882a593Smuzhiyun /**
75*4882a593Smuzhiyun  * struct img_ir_free_timing - timing data for free time symbol
76*4882a593Smuzhiyun  * @minlen:	Minimum number of bits of data
77*4882a593Smuzhiyun  * @maxlen:	Maximum number of bits of data
78*4882a593Smuzhiyun  * @ft_min:	Minimum free time after message
79*4882a593Smuzhiyun  */
80*4882a593Smuzhiyun struct img_ir_free_timing {
81*4882a593Smuzhiyun 	/* measured in bits */
82*4882a593Smuzhiyun 	u8 minlen;
83*4882a593Smuzhiyun 	u8 maxlen;
84*4882a593Smuzhiyun 	u16 ft_min;
85*4882a593Smuzhiyun };
86*4882a593Smuzhiyun 
87*4882a593Smuzhiyun /**
88*4882a593Smuzhiyun  * struct img_ir_timings - Timing values.
89*4882a593Smuzhiyun  * @ldr:	Leader symbol timing data
90*4882a593Smuzhiyun  * @s00:	Zero symbol timing data for primary decoder
91*4882a593Smuzhiyun  * @s01:	One symbol timing data for primary decoder
92*4882a593Smuzhiyun  * @s10:	Zero symbol timing data for secondary (no leader symbol) decoder
93*4882a593Smuzhiyun  * @s11:	One symbol timing data for secondary (no leader symbol) decoder
94*4882a593Smuzhiyun  * @ft:		Free time symbol timing data
95*4882a593Smuzhiyun  */
96*4882a593Smuzhiyun struct img_ir_timings {
97*4882a593Smuzhiyun 	struct img_ir_symbol_timing ldr, s00, s01, s10, s11;
98*4882a593Smuzhiyun 	struct img_ir_free_timing ft;
99*4882a593Smuzhiyun };
100*4882a593Smuzhiyun 
101*4882a593Smuzhiyun /**
102*4882a593Smuzhiyun  * struct img_ir_filter - Filter IR events.
103*4882a593Smuzhiyun  * @data:	Data to match.
104*4882a593Smuzhiyun  * @mask:	Mask of bits to compare.
105*4882a593Smuzhiyun  * @minlen:	Additional minimum number of bits.
106*4882a593Smuzhiyun  * @maxlen:	Additional maximum number of bits.
107*4882a593Smuzhiyun  */
108*4882a593Smuzhiyun struct img_ir_filter {
109*4882a593Smuzhiyun 	u64 data;
110*4882a593Smuzhiyun 	u64 mask;
111*4882a593Smuzhiyun 	u8 minlen;
112*4882a593Smuzhiyun 	u8 maxlen;
113*4882a593Smuzhiyun };
114*4882a593Smuzhiyun 
115*4882a593Smuzhiyun /**
116*4882a593Smuzhiyun  * struct img_ir_timing_regvals - Calculated timing register values.
117*4882a593Smuzhiyun  * @ldr:	Leader symbol timing register value
118*4882a593Smuzhiyun  * @s00:	Zero symbol timing register value for primary decoder
119*4882a593Smuzhiyun  * @s01:	One symbol timing register value for primary decoder
120*4882a593Smuzhiyun  * @s10:	Zero symbol timing register value for secondary decoder
121*4882a593Smuzhiyun  * @s11:	One symbol timing register value for secondary decoder
122*4882a593Smuzhiyun  * @ft:		Free time symbol timing register value
123*4882a593Smuzhiyun  */
124*4882a593Smuzhiyun struct img_ir_timing_regvals {
125*4882a593Smuzhiyun 	u32 ldr, s00, s01, s10, s11, ft;
126*4882a593Smuzhiyun };
127*4882a593Smuzhiyun 
128*4882a593Smuzhiyun #define IMG_IR_SCANCODE		0	/* new scancode */
129*4882a593Smuzhiyun #define IMG_IR_REPEATCODE	1	/* repeat the previous code */
130*4882a593Smuzhiyun 
131*4882a593Smuzhiyun /**
132*4882a593Smuzhiyun  * struct img_ir_scancode_req - Scancode request data.
133*4882a593Smuzhiyun  * @protocol:	Protocol code of received message (defaults to
134*4882a593Smuzhiyun  *		RC_PROTO_UNKNOWN).
135*4882a593Smuzhiyun  * @scancode:	Scan code of received message (must be written by
136*4882a593Smuzhiyun  *		handler if IMG_IR_SCANCODE is returned).
137*4882a593Smuzhiyun  * @toggle:	Toggle bit (defaults to 0).
138*4882a593Smuzhiyun  */
139*4882a593Smuzhiyun struct img_ir_scancode_req {
140*4882a593Smuzhiyun 	enum rc_proto protocol;
141*4882a593Smuzhiyun 	u32 scancode;
142*4882a593Smuzhiyun 	u8 toggle;
143*4882a593Smuzhiyun };
144*4882a593Smuzhiyun 
145*4882a593Smuzhiyun /**
146*4882a593Smuzhiyun  * struct img_ir_decoder - Decoder settings for an IR protocol.
147*4882a593Smuzhiyun  * @type:	Protocol types bitmap.
148*4882a593Smuzhiyun  * @tolerance:	Timing tolerance as a percentage (default 10%).
149*4882a593Smuzhiyun  * @unit:	Unit of timings in nanoseconds (default 1 us).
150*4882a593Smuzhiyun  * @timings:	Primary timings
151*4882a593Smuzhiyun  * @rtimings:	Additional override timings while waiting for repeats.
152*4882a593Smuzhiyun  * @repeat:	Maximum repeat interval (always in milliseconds).
153*4882a593Smuzhiyun  * @control:	Control flags.
154*4882a593Smuzhiyun  *
155*4882a593Smuzhiyun  * @scancode:	Pointer to function to convert the IR data into a scancode (it
156*4882a593Smuzhiyun  *		must be safe to execute in interrupt context).
157*4882a593Smuzhiyun  *		Returns IMG_IR_SCANCODE to emit new scancode.
158*4882a593Smuzhiyun  *		Returns IMG_IR_REPEATCODE to repeat previous code.
159*4882a593Smuzhiyun  *		Returns -errno (e.g. -EINVAL) on error.
160*4882a593Smuzhiyun  * @filter:	Pointer to function to convert scancode filter to raw hardware
161*4882a593Smuzhiyun  *		filter. The minlen and maxlen fields will have been initialised
162*4882a593Smuzhiyun  *		to the maximum range.
163*4882a593Smuzhiyun  */
164*4882a593Smuzhiyun struct img_ir_decoder {
165*4882a593Smuzhiyun 	/* core description */
166*4882a593Smuzhiyun 	u64				type;
167*4882a593Smuzhiyun 	unsigned int			tolerance;
168*4882a593Smuzhiyun 	unsigned int			unit;
169*4882a593Smuzhiyun 	struct img_ir_timings		timings;
170*4882a593Smuzhiyun 	struct img_ir_timings		rtimings;
171*4882a593Smuzhiyun 	unsigned int			repeat;
172*4882a593Smuzhiyun 	struct img_ir_control		control;
173*4882a593Smuzhiyun 
174*4882a593Smuzhiyun 	/* scancode logic */
175*4882a593Smuzhiyun 	int (*scancode)(int len, u64 raw, u64 enabled_protocols,
176*4882a593Smuzhiyun 			struct img_ir_scancode_req *request);
177*4882a593Smuzhiyun 	int (*filter)(const struct rc_scancode_filter *in,
178*4882a593Smuzhiyun 		      struct img_ir_filter *out, u64 protocols);
179*4882a593Smuzhiyun };
180*4882a593Smuzhiyun 
181*4882a593Smuzhiyun extern struct img_ir_decoder img_ir_nec;
182*4882a593Smuzhiyun extern struct img_ir_decoder img_ir_jvc;
183*4882a593Smuzhiyun extern struct img_ir_decoder img_ir_sony;
184*4882a593Smuzhiyun extern struct img_ir_decoder img_ir_sharp;
185*4882a593Smuzhiyun extern struct img_ir_decoder img_ir_sanyo;
186*4882a593Smuzhiyun extern struct img_ir_decoder img_ir_rc5;
187*4882a593Smuzhiyun extern struct img_ir_decoder img_ir_rc6;
188*4882a593Smuzhiyun 
189*4882a593Smuzhiyun /**
190*4882a593Smuzhiyun  * struct img_ir_reg_timings - Reg values for decoder timings at clock rate.
191*4882a593Smuzhiyun  * @ctrl:	Processed control register value.
192*4882a593Smuzhiyun  * @timings:	Processed primary timings.
193*4882a593Smuzhiyun  * @rtimings:	Processed repeat timings.
194*4882a593Smuzhiyun  */
195*4882a593Smuzhiyun struct img_ir_reg_timings {
196*4882a593Smuzhiyun 	u32				ctrl;
197*4882a593Smuzhiyun 	struct img_ir_timing_regvals	timings;
198*4882a593Smuzhiyun 	struct img_ir_timing_regvals	rtimings;
199*4882a593Smuzhiyun };
200*4882a593Smuzhiyun 
201*4882a593Smuzhiyun struct img_ir_priv;
202*4882a593Smuzhiyun 
203*4882a593Smuzhiyun #ifdef CONFIG_IR_IMG_HW
204*4882a593Smuzhiyun 
205*4882a593Smuzhiyun enum img_ir_mode {
206*4882a593Smuzhiyun 	IMG_IR_M_NORMAL,
207*4882a593Smuzhiyun 	IMG_IR_M_REPEATING,
208*4882a593Smuzhiyun #ifdef CONFIG_PM_SLEEP
209*4882a593Smuzhiyun 	IMG_IR_M_WAKE,
210*4882a593Smuzhiyun #endif
211*4882a593Smuzhiyun };
212*4882a593Smuzhiyun 
213*4882a593Smuzhiyun /**
214*4882a593Smuzhiyun  * struct img_ir_priv_hw - Private driver data for hardware decoder.
215*4882a593Smuzhiyun  * @ct_quirks:		Quirk bits for each code type.
216*4882a593Smuzhiyun  * @rdev:		Remote control device
217*4882a593Smuzhiyun  * @clk_nb:		Notifier block for clock notify events.
218*4882a593Smuzhiyun  * @end_timer:		Timer until repeat timeout.
219*4882a593Smuzhiyun  * @suspend_timer:	Timer to re-enable protocol.
220*4882a593Smuzhiyun  * @decoder:		Current decoder settings.
221*4882a593Smuzhiyun  * @enabled_protocols:	Currently enabled protocols.
222*4882a593Smuzhiyun  * @clk_hz:		Current core clock rate in Hz.
223*4882a593Smuzhiyun  * @reg_timings:	Timing reg values for decoder at clock rate.
224*4882a593Smuzhiyun  * @flags:		IMG_IR_F_*.
225*4882a593Smuzhiyun  * @filters:		HW filters (derived from scancode filters).
226*4882a593Smuzhiyun  * @mode:		Current decode mode.
227*4882a593Smuzhiyun  * @stopping:		Indicates that decoder is being taken down and timers
228*4882a593Smuzhiyun  *			should not be restarted.
229*4882a593Smuzhiyun  * @suspend_irqen:	Saved IRQ enable mask over suspend.
230*4882a593Smuzhiyun  * @quirk_suspend_irq:	Saved IRQ enable mask over quirk suspend timer.
231*4882a593Smuzhiyun  */
232*4882a593Smuzhiyun struct img_ir_priv_hw {
233*4882a593Smuzhiyun 	unsigned int			ct_quirks[4];
234*4882a593Smuzhiyun 	struct rc_dev			*rdev;
235*4882a593Smuzhiyun 	struct notifier_block		clk_nb;
236*4882a593Smuzhiyun 	struct timer_list		end_timer;
237*4882a593Smuzhiyun 	struct timer_list		suspend_timer;
238*4882a593Smuzhiyun 	const struct img_ir_decoder	*decoder;
239*4882a593Smuzhiyun 	u64				enabled_protocols;
240*4882a593Smuzhiyun 	unsigned long			clk_hz;
241*4882a593Smuzhiyun 	struct img_ir_reg_timings	reg_timings;
242*4882a593Smuzhiyun 	unsigned int			flags;
243*4882a593Smuzhiyun 	struct img_ir_filter		filters[RC_FILTER_MAX];
244*4882a593Smuzhiyun 
245*4882a593Smuzhiyun 	enum img_ir_mode		mode;
246*4882a593Smuzhiyun 	bool				stopping;
247*4882a593Smuzhiyun 	u32				suspend_irqen;
248*4882a593Smuzhiyun 	u32				quirk_suspend_irq;
249*4882a593Smuzhiyun };
250*4882a593Smuzhiyun 
img_ir_hw_enabled(struct img_ir_priv_hw * hw)251*4882a593Smuzhiyun static inline bool img_ir_hw_enabled(struct img_ir_priv_hw *hw)
252*4882a593Smuzhiyun {
253*4882a593Smuzhiyun 	return hw->rdev;
254*4882a593Smuzhiyun };
255*4882a593Smuzhiyun 
256*4882a593Smuzhiyun void img_ir_isr_hw(struct img_ir_priv *priv, u32 irq_status);
257*4882a593Smuzhiyun void img_ir_setup_hw(struct img_ir_priv *priv);
258*4882a593Smuzhiyun int img_ir_probe_hw(struct img_ir_priv *priv);
259*4882a593Smuzhiyun void img_ir_remove_hw(struct img_ir_priv *priv);
260*4882a593Smuzhiyun 
261*4882a593Smuzhiyun #ifdef CONFIG_PM_SLEEP
262*4882a593Smuzhiyun int img_ir_suspend(struct device *dev);
263*4882a593Smuzhiyun int img_ir_resume(struct device *dev);
264*4882a593Smuzhiyun #else
265*4882a593Smuzhiyun #define img_ir_suspend NULL
266*4882a593Smuzhiyun #define img_ir_resume NULL
267*4882a593Smuzhiyun #endif
268*4882a593Smuzhiyun 
269*4882a593Smuzhiyun #else
270*4882a593Smuzhiyun 
271*4882a593Smuzhiyun struct img_ir_priv_hw {
272*4882a593Smuzhiyun };
273*4882a593Smuzhiyun 
img_ir_hw_enabled(struct img_ir_priv_hw * hw)274*4882a593Smuzhiyun static inline bool img_ir_hw_enabled(struct img_ir_priv_hw *hw)
275*4882a593Smuzhiyun {
276*4882a593Smuzhiyun 	return false;
277*4882a593Smuzhiyun };
img_ir_isr_hw(struct img_ir_priv * priv,u32 irq_status)278*4882a593Smuzhiyun static inline void img_ir_isr_hw(struct img_ir_priv *priv, u32 irq_status)
279*4882a593Smuzhiyun {
280*4882a593Smuzhiyun }
img_ir_setup_hw(struct img_ir_priv * priv)281*4882a593Smuzhiyun static inline void img_ir_setup_hw(struct img_ir_priv *priv)
282*4882a593Smuzhiyun {
283*4882a593Smuzhiyun }
img_ir_probe_hw(struct img_ir_priv * priv)284*4882a593Smuzhiyun static inline int img_ir_probe_hw(struct img_ir_priv *priv)
285*4882a593Smuzhiyun {
286*4882a593Smuzhiyun 	return -ENODEV;
287*4882a593Smuzhiyun }
img_ir_remove_hw(struct img_ir_priv * priv)288*4882a593Smuzhiyun static inline void img_ir_remove_hw(struct img_ir_priv *priv)
289*4882a593Smuzhiyun {
290*4882a593Smuzhiyun }
291*4882a593Smuzhiyun 
292*4882a593Smuzhiyun #define img_ir_suspend NULL
293*4882a593Smuzhiyun #define img_ir_resume NULL
294*4882a593Smuzhiyun 
295*4882a593Smuzhiyun #endif /* CONFIG_IR_IMG_HW */
296*4882a593Smuzhiyun 
297*4882a593Smuzhiyun #endif /* _IMG_IR_HW_H_ */
298