Searched +full:tegra210 +full:- +full:pmc (Results 1 – 23 of 23) sorted by relevance
1 # SPDX-License-Identifier: GPL-2.03 ---4 $id: http://devicetree.org/schemas/arm/tegra/nvidia,tegra20-pmc.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#7 title: Tegra Power Management Controller (PMC)10 - Thierry Reding <thierry.reding@gmail.com>11 - Jonathan Hunter <jonathanh@nvidia.com>16 - nvidia,tegra20-pmc17 - nvidia,tegra20-pmc18 - nvidia,tegra30-pmc[all …]
1 // SPDX-License-Identifier: GPL-2.02 #include "tegra210.dtsi"5 model = "NVIDIA Tegra210 P2530 main board";6 compatible = "nvidia,p2530", "nvidia,tegra210";14 stdout-path = "serial0:115200n8";29 clock-frequency = <400000>;32 pmc@7000e400 {33 nvidia,invert-interrupt;39 bus-width = <8>;40 non-removable;[all …]
1 // SPDX-License-Identifier: GPL-2.02 #include <dt-bindings/clock/tegra186-clock.h>3 #include <dt-bindings/gpio/tegra186-gpio.h>4 #include <dt-bindings/interrupt-controller/arm-gic.h>5 #include <dt-bindings/mailbox/tegra186-hsp.h>6 #include <dt-bindings/memory/tegra186-mc.h>7 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>8 #include <dt-bindings/power/tegra186-powergate.h>9 #include <dt-bindings/reset/tegra186-reset.h>10 #include <dt-bindings/thermal/tegra186-bpmp-thermal.h>[all …]
1 // SPDX-License-Identifier: GPL-2.02 #include <dt-bindings/clock/tegra210-car.h>3 #include <dt-bindings/gpio/tegra-gpio.h>4 #include <dt-bindings/memory/tegra210-mc.h>5 #include <dt-bindings/pinctrl/pinctrl-tegra.h>6 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>7 #include <dt-bindings/reset/tegra210-car.h>8 #include <dt-bindings/interrupt-controller/arm-gic.h>9 #include <dt-bindings/thermal/tegra124-soctherm.h>10 #include <dt-bindings/soc/tegra-pmc.h>[all …]
1 // SPDX-License-Identifier: GPL-2.02 #include <dt-bindings/clock/tegra194-clock.h>3 #include <dt-bindings/gpio/tegra194-gpio.h>4 #include <dt-bindings/interrupt-controller/arm-gic.h>5 #include <dt-bindings/mailbox/tegra186-hsp.h>6 #include <dt-bindings/pinctrl/pinctrl-tegra.h>7 #include <dt-bindings/power/tegra194-powergate.h>8 #include <dt-bindings/reset/tegra194-reset.h>9 #include <dt-bindings/thermal/tegra194-bpmp-thermal.h>10 #include <dt-bindings/memory/tegra194-mc.h>[all …]
1 // SPDX-License-Identifier: GPL-2.02 #include <dt-bindings/mfd/max77620.h>4 #include "tegra210.dtsi"8 compatible = "nvidia,p2180", "nvidia,tegra210";17 stdout-path = "serial0:115200n8";26 vdd-supply = <&vdd_gpu>;36 clock-frequency = <400000>;41 interrupt-parent = <&tegra_pmc>;44 #interrupt-cells = <2>;45 interrupt-controller;[all …]
1 // SPDX-License-Identifier: GPL-2.02 /dts-v1/;4 #include <dt-bindings/input/gpio-keys.h>5 #include <dt-bindings/input/linux-event-codes.h>6 #include <dt-bindings/mfd/max77620.h>8 #include "tegra210.dtsi"12 compatible = "nvidia,p3450-0000", "nvidia,tegra210";22 stdout-path = "serial0:115200n8";33 avdd-pll-uerefe-supply = <&vdd_pex_1v05>;34 hvddio-pex-supply = <&vdd_1v8>;[all …]
1 // SPDX-License-Identifier: GPL-2.02 /dts-v1/;4 #include <dt-bindings/input/input.h>5 #include <dt-bindings/mfd/max77620.h>6 #include <dt-bindings/pinctrl/pinctrl-tegra.h>8 #include "tegra210.dtsi"12 compatible = "google,smaug-rev8", "google,smaug-rev7",13 "google,smaug-rev6", "google,smaug-rev5",14 "google,smaug-rev4", "google,smaug-rev3",15 "google,smaug-rev2", "google,smaug-rev1",[all …]
1 // SPDX-License-Identifier: GPL-2.03 #include <dt-bindings/input/input.h>4 #include <dt-bindings/input/gpio-keys.h>5 #include <dt-bindings/mfd/max77620.h>6 #include <dt-bindings/pinctrl/pinctrl-tegra.h>7 #include "tegra210.dtsi"16 stdout-path = "serial0:115200n8";26 pinctrl-names = "boot";27 pinctrl-0 = <&state_boot>;35 nvidia,enable-input = <TEGRA_PIN_DISABLE>;[all …]
1 #include <dt-bindings/clock/tegra210-car.h>2 #include <dt-bindings/gpio/tegra-gpio.h>3 #include <dt-bindings/memory/tegra210-mc.h>4 #include <dt-bindings/pinctrl/pinctrl-tegra.h>5 #include <dt-bindings/interrupt-controller/arm-gic.h>6 #include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>9 compatible = "nvidia,tegra210";10 interrupt-parent = <&lic>;11 #address-cells = <2>;12 #size-cells = <2>;[all …]
8 --------------------9 - compatible: Must be:10 - Tegra124: "nvidia,tegra124-xusb"11 - Tegra132: "nvidia,tegra132-xusb", "nvidia,tegra124-xusb"12 - Tegra210: "nvidia,tegra210-xusb"13 - Tegra186: "nvidia,tegra186-xusb"14 - reg: Must contain the base and length of the xHCI host registers, XUSB FPCI16 - reg-names: Must contain the following entries:17 - "hcd"18 - "fpci"[all …]
1 // SPDX-License-Identifier: GPL-2.0-only3 * Copyright (c) 2012-2014 NVIDIA CORPORATION. All rights reserved.8 #include <linux/clk-provider.h>17 #include <dt-bindings/clock/tegra210-car.h>18 #include <dt-bindings/reset/tegra210-car.h>20 #include <soc/tegra/pmc.h>23 #include "clk-id.h"27 * banks present in the Tegra210 CAR IP block. The banks are264 * SDM fractional divisor is 16-bit 2's complement signed number within265 * (-2^12 ... 2^12-1) range. Represented in PLL data structure as unsigned[all …]
2 * (C) Copyright 2010-20155 * SPDX-License-Identifier: GPL-2.0+17 #include <asm/arch-tegra/ap.h>18 #include <asm/arch-tegra/board.h>19 #include <asm/arch-tegra/pmc.h>20 #include <asm/arch-tegra/sys_proto.h>21 #include <asm/arch-tegra/warmboot.h>59 * This register reads 0xffffffff in non-secure mode. This register in tegra_cpu_is_non_secure()62 * non-secure mode. in tegra_cpu_is_non_secure()65 uint32_t mc_s_cfg0 = readl(&mc->mc_security_cfg0); in tegra_cpu_is_non_secure()[all …]
2 * Copyright (c) 2010-2015, NVIDIA CORPORATION. All rights reserved.4 * SPDX-License-Identifier: GPL-2.016 #include <asm/arch-tegra/ap.h>17 #include <asm/arch-tegra/clk_rst.h>18 #include <asm/arch-tegra/pmc.h>19 #include <asm/arch-tegra/timer.h>67 reg = readl(&clkrst->crc_osc_ctrl); in clock_get_osc_bypass()82 return &clkrst->crc_pll[clkid]; in get_pll()101 return -1; in clock_ll_read_pll()102 data = readl(&pll->pll_base); in clock_ll_read_pll()[all …]
1 // SPDX-License-Identifier: GPL-2.0-only8 #include <linux/dma-mapping.h>19 #include <soc/tegra/pmc.h>53 writel(value, vic->regs + offset); in vic_writel()61 err = clk_prepare_enable(vic->clk); in vic_runtime_resume()67 err = reset_control_deassert(vic->rst); in vic_runtime_resume()76 clk_disable_unprepare(vic->clk); in vic_runtime_resume()85 err = reset_control_assert(vic->rst); in vic_runtime_suspend()91 clk_disable_unprepare(vic->clk); in vic_runtime_suspend()93 vic->booted = false; in vic_runtime_suspend()[all …]
1 // SPDX-License-Identifier: GPL-2.0-only7 #include <linux/clk-provider.h>17 #include <soc/tegra/pmc.h>486 u32 value = readl(sor->regs + (offset << 2)); in tegra_sor_readl()488 trace_sor_readl(sor->dev, offset, value); in tegra_sor_readl()496 trace_sor_writel(sor->dev, offset, value); in tegra_sor_writel()497 writel(value, sor->regs + (offset << 2)); in tegra_sor_writel()504 clk_disable_unprepare(sor->clk); in tegra_sor_set_parent_clock()506 err = clk_set_parent(sor->clk_out, parent); in tegra_sor_set_parent_clock()510 err = clk_prepare_enable(sor->clk); in tegra_sor_set_parent_clock()[all …]
1 // SPDX-License-Identifier: GPL-2.0-only16 #include <soc/tegra/pmc.h>36 stats->frames = 0; in tegra_dc_stats_reset()37 stats->vblank = 0; in tegra_dc_stats_reset()38 stats->underflow = 0; in tegra_dc_stats_reset()39 stats->overflow = 0; in tegra_dc_stats_reset()58 offset = 0x000 + (offset - 0x500); in tegra_plane_offset()59 return plane->offset + offset; in tegra_plane_offset()63 offset = 0x180 + (offset - 0x700); in tegra_plane_offset()64 return plane->offset + offset; in tegra_plane_offset()[all …]
1 // SPDX-License-Identifier: GPL-2.0-only3 * drivers/soc/tegra/pmc.c6 * Copyright (c) 2018-2020, NVIDIA CORPORATION. All rights reserved.12 #define pr_fmt(fmt) "tegra-pmc: " fmt14 #include <linux/arm-smccc.h>16 #include <linux/clk-provider.h>18 #include <linux/clk/clk-conf.h>36 #include <linux/pinctrl/pinconf-generic.h>49 #include <soc/tegra/pmc.h>51 #include <dt-bindings/interrupt-controller/arm-gic.h>[all …]
1 // SPDX-License-Identifier: GPL-2.0-only21 #include <soc/tegra/pmc.h>25 #define DRV_NAME "tegra-ahci"179 struct tegra_ahci_priv *tegra = hpriv->plat_data; in tegra_ahci_handle_quirks()182 if (tegra->sata_aux_regs && !tegra->soc->supports_devslp) { in tegra_ahci_handle_quirks()183 val = readl(tegra->sata_aux_regs + SATA_AUX_MISC_CNTL_1_0); in tegra_ahci_handle_quirks()185 writel(val, tegra->sata_aux_regs + SATA_AUX_MISC_CNTL_1_0); in tegra_ahci_handle_quirks()191 struct tegra_ahci_priv *tegra = hpriv->plat_data; in tegra124_ahci_init()203 writel(BIT(0), tegra->sata_regs + SCFG_OFFSET + T_SATA0_INDEX); in tegra124_ahci_init()205 val = readl(tegra->sata_regs + in tegra124_ahci_init()[all …]
1 // SPDX-License-Identifier: GPL-2.011 #include <linux/dma-mapping.h>30 #include <soc/tegra/pmc.h>280 return readl(tegra->fpci_base + offset); in fpci_readl()286 writel(value, tegra->fpci_base + offset); in fpci_writel()291 return readl(tegra->ipfs_base + offset); in ipfs_readl()297 writel(value, tegra->ipfs_base + offset); in ipfs_writel()324 struct clk *clk = tegra->ss_src_clk; in tegra_xusb_set_ss_clk()338 new_parent_rate = clk_get_rate(tegra->pll_u_480m); in tegra_xusb_set_ss_clk()345 err = clk_set_parent(clk, tegra->pll_u_480m); in tegra_xusb_set_ss_clk()[all …]
1 // SPDX-License-Identifier: GPL-2.0+9 * Copyright (c) 2008-2009, NVIDIA Corporation.11 * Bits taken from arch/arm/mach-dove/pcie.c43 #include <soc/tegra/pmc.h>270 * Fields in PADS_REFCLK_CFG*. Those registers form an array of 16-bit397 writel(value, pcie->afi + offset); in afi_writel()402 return readl(pcie->afi + offset); in afi_readl()408 writel(value, pcie->pads + offset); in pads_writel()413 return readl(pcie->pads + offset); in pads_readl()448 struct tegra_pcie *pcie = bus->sysdata; in tegra_pcie_map_bus()[all …]
1 // SPDX-License-Identifier: GPL-2.0-only21 #include <media/v4l2-event.h>22 #include <media/v4l2-fh.h>23 #include <media/v4l2-fwnode.h>24 #include <media/v4l2-ioctl.h>25 #include <media/videobuf2-dma-contig.h>27 #include <soc/tegra/pmc.h>68 for (i = offset; i < vi->soc->nformats; ++i) { in tegra_get_format_idx_by_code()69 if (vi->soc->video_formats[i].code == code) in tegra_get_format_idx_by_code()73 return -1; in tegra_get_format_idx_by_code()[all …]
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