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/OK3568_Linux_fs/kernel/Documentation/timers/
H A Dtimekeeping.rst2 Clock sources, Clock events, sched_clock() and delay timers
10 If you grep through the kernel source you will find a number of architecture-
11 specific implementations of clock sources, clockevents and several likewise
12 architecture-specific overrides of the sched_clock() function and some
15 To provide timekeeping for your platform, the clock source provides
16 the basic timeline, whereas clock events shoot interrupts on certain points
17 on this timeline, providing facilities such as high-resolution timers.
22 Clock sources
23 -------------
25 The purpose of the clock source is to provide a timeline for the system that
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/OK3568_Linux_fs/kernel/arch/sparc/include/asm/
H A Dbbc.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * bbc.h: Defines for BootBus Controller found on UltraSPARC-III
12 /* Register sizes are indicated by "B" (Byte, 1-byte),
13 * "H" (Half-word, 2 bytes), "W" (Word, 4 bytes) or
26 #define BBC_CSC 0x0d /* [B] Clock Synthesizers Control*/
29 #define BBC_ES_DACT 0x14 /* [B] E* De-Assert Change Time */
30 #define BBC_ES_DABT 0x15 /* [B] E* De-Assert Bypass Time */
33 #define BBC_ES_FSL 0x1c /* [W] E* Frequency Switch Latency*/
38 #define BBC_I2C_0_S1 0x2e /* [B] I2C ctrlr-0 reg S1 */
39 #define BBC_I2C_0_S0 0x2f /* [B] I2C ctrlr-0 regs S0,S0',S2,S3*/
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/OK3568_Linux_fs/kernel/arch/powerpc/include/asm/
H A Dmpc5121.h1 /* SPDX-License-Identifier: GPL-2.0-only */
23 * Clock Control Module
26 u32 spmr; /* System PLL Mode Register */
27 u32 sccr1; /* System Clock Control Register 1 */
28 u32 sccr2; /* System Clock Control Register 2 */
29 u32 scfr1; /* System Clock Frequency Register 1 */
30 u32 scfr2; /* System Clock Frequency Register 2 */
31 u32 scfr2s; /* System Clock Frequency Shadow Register 2 */
33 u32 psc_ccr[12]; /* PSC Clock Control Registers */
34 u32 spccr; /* SPDIF Clock Control Register */
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/OK3568_Linux_fs/kernel/include/linux/
H A Dptp_clock_kernel.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * PTP 1588 clock support
31 * struct ptp_system_timestamp - system time corresponding to a PHC timestamp
39 * struct ptp_clock_info - describes a PTP hardware clock
41 * @owner: The clock driver should set to THIS_MODULE.
42 * @name: A short "friendly name" to identify the clock and to
45 * @max_adj: The maximum possible frequency adjustment, in parts per billon.
50 * @pps: Indicates whether the clock supports a PPS callback.
55 * clock operations
57 * @adjfine: Adjusts the frequency of the hardware clock.
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/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/clock/
H A Dqoriq-clock.txt1 * Clock Block on Freescale QorIQ Platforms
4 SYSCLK signal. The SYSCLK input (frequency) is multiplied using
14 --------------- -------------
18 1. Clock Block Binding
21 - compatible: Should contain a chip-specific clock block compatible
22 string and (if applicable) may contain a chassis-version clock
25 Chip-specific strings are of the form "fsl,<chip>-clockgen", such as:
26 * "fsl,p2041-clockgen"
27 * "fsl,p3041-clockgen"
28 * "fsl,p4080-clockgen"
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H A Dlpc1850-cgu.txt1 * NXP LPC1850 Clock Generation Unit (CGU)
4 peripheral blocks of the LPC18xx. Each independent clock is called
5 a base clock and itself is one of the inputs to the two Clock
9 The CGU selects the inputs to the clock generators from multiple
10 clock sources, controls the clock generation, and routes the outputs
11 of the clock generators through the clock source bus to the output
12 stages. Each output stage provides an independent clock source and
15 - Above text taken from NXP LPC1850 User Manual.
18 This binding uses the common clock binding:
19 Documentation/devicetree/bindings/clock/clock-bindings.txt
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H A Drenesas,emev2-smu.txt1 Device tree Clock bindings for Renesas EMMA Mobile EV2
3 This binding uses the common clock binding.
6 System Management Unit described in user's manual R19UH0037EJ1000_SMU.
7 This is not a clock provider, but clocks under SMU depend on it.
10 - compatible: Should be "renesas,emev2-smu"
11 - reg: Address and Size of SMU registers
15 "Serial clock generator" in fig."Clock System Overview" of the manual,
16 and "xxx frequency division setting register" (XXXCLKDIV) registers.
17 This makes internal (neither input nor output) clock that is provided
21 - compatible: Should be "renesas,emev2-smu-clkdiv"
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/OK3568_Linux_fs/kernel/drivers/net/ethernet/intel/e1000e/
H A Dptp.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
4 /* PTP 1588 Hardware Clock (PHC)
5 * Derived from PTP Hardware Clock driver for Intel 82576 and 82580 (igb)
18 * e1000e_phc_adjfreq - adjust the frequency of the hardware clock
19 * @ptp: ptp clock structure
20 * @delta: Desired frequency change in parts per billion
22 * Adjust the frequency of the PHC cycle counter by the indicated delta from
23 * the base frequency.
29 struct e1000_hw *hw = &adapter->hw; in e1000e_phc_adjfreq()
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/OK3568_Linux_fs/kernel/drivers/cpufreq/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
2 menu "CPU Frequency scaling"
5 bool "CPU Frequency scaling"
8 CPU Frequency scaling allows you to change the clock speed of
10 the lower the CPU clock speed, the less power the CPU consumes.
13 clock speed, you need to either enable a dynamic cpufreq governor
16 For details, take a look at <file:Documentation/cpu-freq>.
31 bool "CPU frequency transition statistics"
33 Export CPU frequency statistics information through sysfs.
38 bool "CPU frequency time-in-state statistics"
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/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/ptp/
H A Dptp-qoriq.txt1 * Freescale QorIQ 1588 timer based PTP clock
5 - compatible Should be "fsl,etsec-ptp" for eTSEC
6 Should be "fsl,fman-ptp-timer" for DPAA FMan
7 Should be "fsl,dpaa2-ptp" for DPAA2
8 Should be "fsl,enetc-ptp" for ENETC
9 - reg Offset and length of the register set for the device
10 - interrupts There should be at least two interrupts. Some devices
13 Clock Properties:
15 - fsl,cksel Timer reference clock source.
16 - fsl,tclk-period Timer reference clock period in nanoseconds.
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/OK3568_Linux_fs/u-boot/arch/m68k/cpu/mcf532x/
H A Dspeed.c3 * (C) Copyright 2000-2003
6 * Copyright (C) 2004-2008, 2012 Freescale Semiconductor, Inc.
7 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
9 * SPDX-License-Identifier: GPL-2.0+
50 /* Get the value of the current system clock */
58 if (in_be16(&ccm->misccr) & CCM_MISCCR_LIMP) { in get_sys_clock()
59 divider = in_be16(&ccm->cdr) & CCM_CDR_LPDIV(0xF); in get_sys_clock()
68 u32 pfdr = (in_be32(&pll->pcr) & 0x3F) + 1; in get_sys_clock()
69 u32 refdiv = (1 << ((in_be32(&pll->pcr) & PLL_PCR_REFDIV(7)) >> 8)); in get_sys_clock()
70 u32 busdiv = ((in_be32(&pll->pdr) & 0x00F0) >> 4) + 1; in get_sys_clock()
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/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/timer/
H A Dbrcm,bcm2835-system-timer.txt1 BCM2835 System Timer
3 The System Timer peripheral provides four 32-bit timer channels and a
4 single 64-bit free running counter. Each channel has an output compare
10 - compatible : should be "brcm,bcm2835-system-timer"
11 - reg : Specifies base physical address and size of the registers.
12 - interrupts : A list of 4 interrupt sinks; one per timer channel.
13 - clock-frequency : The frequency of the clock that drives the counter, in Hz.
18 compatible = "brcm,bcm2835-system-timer";
21 clock-frequency = <1000000>;
/OK3568_Linux_fs/u-boot/arch/arm/cpu/armv7/ls102xa/
H A Dfdt.c4 * SPDX-License-Identifier: GPL-2.0+
12 #include <asm/arch/clock.h>
44 priv = dev->priv; in ft_fixup_enet_phy_connect_type()
45 if (priv->flags & TSEC_SGMII) in ft_fixup_enet_phy_connect_type()
63 "phy-handle", ph, 1); in ft_fixup_enet_phy_connect_type()
65 do_fixup_by_path(fdt, enet_path, "phy-connection-type", in ft_fixup_enet_phy_connect_type()
81 svr = in_be32(&gur->svr); in ft_cpu_setup()
85 /* delete crypto node if not on an E-processor */ in ft_cpu_setup()
93 fdt_fixup_crypto_node(blob, sec_in32(&sec->secvid_ms)); in ft_cpu_setup()
97 off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4); in ft_cpu_setup()
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/OK3568_Linux_fs/kernel/drivers/gpu/arm/bifrost/
H A Dmali_kbase_config_defaults.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
4 * (C) COPYRIGHT 2013-2023 ARM Limited. All rights reserved.
18 * http://www.gnu.org/licenses/gpl-2.0.html.
102 * -# Power off one or more shader cores
103 * -# Power off the entire GPU
113 #define DEFAULT_PM_POWEROFF_TICK_SHADER (2) /* 400-800us */
121 /* Default minimum number of scheduling ticks before jobs are soft-stopped.
123 * This defines the time-slice for a job (which may be different from that of a
126 #define DEFAULT_JS_SOFT_STOP_TICKS (1) /* 100ms-200ms */
128 /* Default minimum number of scheduling ticks before CL jobs are soft-stopped. */
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/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/memory-controllers/
H A Dnvidia,tegra30-mc.yaml1 # SPDX-License-Identifier: (GPL-2.0)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra30-mc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Dmitry Osipenko <digetx@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
12 - Thierry Reding <thierry.reding@gmail.com>
18 clock from a group of clients. Typically, a system has a single Arbitration
20 Arbitration Domains to increase the effective system bandwidth.
22 Protocol Arbiter, which manage a related pool of memory devices. A system
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H A Dnvidia,tegra20-emc.txt4 - name : Should be emc
5 - #address-cells : Should be 1
6 - #size-cells : Should be 0
7 - compatible : Should contain "nvidia,tegra20-emc".
8 - reg : Offset and length of the register set for the device
9 - nvidia,use-ram-code : If present, the sub-nodes will be addressed
12 irrespective of ram-code configuration.
13 - interrupts : Should contain EMC General interrupt.
14 - clocks : Should contain EMC clock.
16 Child device nodes describe the memory settings for different configurations and clock rates.
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/OK3568_Linux_fs/kernel/Documentation/ABI/testing/
H A Dsysfs-devices-system-cpu1 What: /sys/devices/system/cpu/
2 Date: pre-git history
3 Contact: Linux kernel mailing list <linux-kernel@vger.kernel.org>
10 /sys/devices/system/cpu/cpu#/
12 What: /sys/devices/system/cpu/kernel_max
13 /sys/devices/system/cpu/offline
14 /sys/devices/system/cpu/online
15 /sys/devices/system/cpu/possible
16 /sys/devices/system/cpu/present
18 Contact: Linux kernel mailing list <linux-kernel@vger.kernel.org>
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/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/mfd/
H A Dcirrus,lochnagar.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - patches@opensource.cirrus.com
15 Logic devices on mini-cards, as well as allowing connection of
17 platform. Audio system topology, clocking and power can all be
25 [2] include/dt-bindings/pinctrl/lochnagar.h
26 [3] include/dt-bindings/clock/lochnagar.h
28 And these documents for the required sub-node binding details:
29 [4] Clock: ../clock/cirrus,lochnagar.yaml
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/OK3568_Linux_fs/u-boot/arch/arm/dts/
H A Duniphier-ld4.dtsi4 * Copyright (C) 2015-2016 Socionext Inc.
7 * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
11 compatible = "socionext,uniphier-ld4";
12 #address-cells = <1>;
13 #size-cells = <1>;
16 #address-cells = <1>;
17 #size-cells = <0>;
21 compatible = "arm,cortex-a9";
23 enable-method = "psci";
24 next-level-cache = <&l2>;
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H A Duniphier-sld8.dtsi4 * Copyright (C) 2015-2016 Socionext Inc.
7 * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
11 compatible = "socionext,uniphier-sld8";
12 #address-cells = <1>;
13 #size-cells = <1>;
16 #address-cells = <1>;
17 #size-cells = <0>;
21 compatible = "arm,cortex-a9";
23 enable-method = "psci";
24 next-level-cache = <&l2>;
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H A Duniphier-pro5.dtsi4 * Copyright (C) 2015-2016 Socionext Inc.
7 * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
11 compatible = "socionext,uniphier-pro5";
12 #address-cells = <1>;
13 #size-cells = <1>;
16 #address-cells = <1>;
17 #size-cells = <0>;
21 compatible = "arm,cortex-a9";
24 enable-method = "psci";
25 next-level-cache = <&l2>;
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/OK3568_Linux_fs/u-boot/doc/
H A DREADME.Heterogeneous-SoCs7 SC3900/DSP cores and such devices like CPRI, MAPLE, MAPLE-ULB etc.
10 Heterogeneous SoCs which are chasis-2 compliant like B4860 and B4420
17 - arch/powerpc/cpu/mpc85xx/cpu.c
22 - arch/powerpc/cpu/mpc85xx/speed.c
25 required cores and devices from RCW and System frequency
27 - arch/powerpc/cpu/mpc8xxx/cpu.c
29 Added API to get the number of SC cores in running system and Their BIT
32 - arch/powerpc/include/asm/config_mpc85xx.h
35 in the system and CONFIGS for SC3900/DSP components
37 - arch/powerpc/include/asm/processor.h
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/OK3568_Linux_fs/kernel/drivers/firmware/
H A Dti_sci.h1 /* SPDX-License-Identifier: BSD-3-Clause */
3 * Texas Instruments System Control Interface (TISCI) Protocol
6 * The system works in a message response protocol
9 * Copyright (C) 2015-2016 Texas Instruments Incorporated - https://www.ti.com/
28 /* Clock requests */
54 /* PSI-L requests */
83 * struct ti_sci_msg_hdr - Generic Message Header for All messages and responses
104 * struct ti_sci_msg_resp_version - Response for a message
126 * struct ti_sci_msg_req_reboot - Reboot the SoC
137 * struct ti_sci_msg_req_set_device_state - Set the desired state of the device
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/OK3568_Linux_fs/kernel/Documentation/virt/kvm/
H A Dtimekeeping.rst1 .. SPDX-License-Identifier: GPL-2.0
4 Timekeeping Virtualization for X86-Based Architectures
32 information relevant to KVM and hardware-based virtualization.
38 KVM clock are special enough to warrant a full exposition and are described in
41 2.1. i8254 - PIT
42 ----------------
45 or PIT. The PIT has a fixed frequency 1.193182 MHz base clock and three
46 channels which can be programmed to deliver periodic or one-shot interrupts.
53 The PIT uses I/O ports 0x40 - 0x43. Access to the 16-bit counters is done
59 -------------- ----------------
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/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/net/wireless/
H A Dti,wlcore.txt5 connects the device to the system.
8 - compatible: should be one of the following:
20 - interrupts : specifies attributes for the out-of-band interrupt.
23 - ref-clock-frequency : ref clock frequency in Hz
24 - tcxo-clock-frequency : tcxo clock frequency in Hz
26 Note: the *-clock-frequency properties assume internal clocks. In case of external
27 clock, new bindings (for parsing the clock nodes) have to be added.
32 vmmc-supply = <&wlan_en_reg>;
33 bus-width = <4>;
34 cap-power-off-card;
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