xref: /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/ptp/ptp-qoriq.txt (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun* Freescale QorIQ 1588 timer based PTP clock
2*4882a593Smuzhiyun
3*4882a593SmuzhiyunGeneral Properties:
4*4882a593Smuzhiyun
5*4882a593Smuzhiyun  - compatible   Should be "fsl,etsec-ptp" for eTSEC
6*4882a593Smuzhiyun                 Should be "fsl,fman-ptp-timer" for DPAA FMan
7*4882a593Smuzhiyun                 Should be "fsl,dpaa2-ptp" for DPAA2
8*4882a593Smuzhiyun                 Should be "fsl,enetc-ptp" for ENETC
9*4882a593Smuzhiyun  - reg          Offset and length of the register set for the device
10*4882a593Smuzhiyun  - interrupts   There should be at least two interrupts. Some devices
11*4882a593Smuzhiyun                 have as many as four PTP related interrupts.
12*4882a593Smuzhiyun
13*4882a593SmuzhiyunClock Properties:
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15*4882a593Smuzhiyun  - fsl,cksel        Timer reference clock source.
16*4882a593Smuzhiyun  - fsl,tclk-period  Timer reference clock period in nanoseconds.
17*4882a593Smuzhiyun  - fsl,tmr-prsc     Prescaler, divides the output clock.
18*4882a593Smuzhiyun  - fsl,tmr-add      Frequency compensation value.
19*4882a593Smuzhiyun  - fsl,tmr-fiper1   Fixed interval period pulse generator.
20*4882a593Smuzhiyun  - fsl,tmr-fiper2   Fixed interval period pulse generator.
21*4882a593Smuzhiyun  - fsl,tmr-fiper3   Fixed interval period pulse generator.
22*4882a593Smuzhiyun                     Supported only on DPAA2 and ENETC hardware.
23*4882a593Smuzhiyun  - fsl,max-adj      Maximum frequency adjustment in parts per billion.
24*4882a593Smuzhiyun  - fsl,extts-fifo   The presence of this property indicates hardware
25*4882a593Smuzhiyun		     support for the external trigger stamp FIFO.
26*4882a593Smuzhiyun  - little-endian    The presence of this property indicates the 1588 timer
27*4882a593Smuzhiyun		     IP block is little-endian mode. The default endian mode
28*4882a593Smuzhiyun		     is big-endian.
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun  These properties set the operational parameters for the PTP
31*4882a593Smuzhiyun  clock. You must choose these carefully for the clock to work right.
32*4882a593Smuzhiyun  Here is how to figure good values:
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun  TimerOsc     = selected reference clock   MHz
35*4882a593Smuzhiyun  tclk_period  = desired clock period       nanoseconds
36*4882a593Smuzhiyun  NominalFreq  = 1000 / tclk_period         MHz
37*4882a593Smuzhiyun  FreqDivRatio = TimerOsc / NominalFreq     (must be greater that 1.0)
38*4882a593Smuzhiyun  tmr_add      = ceil(2^32 / FreqDivRatio)
39*4882a593Smuzhiyun  OutputClock  = NominalFreq / tmr_prsc     MHz
40*4882a593Smuzhiyun  PulseWidth   = 1 / OutputClock            microseconds
41*4882a593Smuzhiyun  FiperFreq1   = desired frequency in Hz
42*4882a593Smuzhiyun  FiperDiv1    = 1000000 * OutputClock / FiperFreq1
43*4882a593Smuzhiyun  tmr_fiper1   = tmr_prsc * tclk_period * FiperDiv1 - tclk_period
44*4882a593Smuzhiyun  max_adj      = 1000000000 * (FreqDivRatio - 1.0) - 1
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun  The calculation for tmr_fiper2 is the same as for tmr_fiper1. The
47*4882a593Smuzhiyun  driver expects that tmr_fiper1 will be correctly set to produce a 1
48*4882a593Smuzhiyun  Pulse Per Second (PPS) signal, since this will be offered to the PPS
49*4882a593Smuzhiyun  subsystem to synchronize the Linux clock.
50*4882a593Smuzhiyun
51*4882a593Smuzhiyun  Reference clock source is determined by the value, which is holded
52*4882a593Smuzhiyun  in CKSEL bits in TMR_CTRL register. "fsl,cksel" property keeps the
53*4882a593Smuzhiyun  value, which will be directly written in those bits, that is why,
54*4882a593Smuzhiyun  according to reference manual, the next clock sources can be used:
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun  For eTSEC,
57*4882a593Smuzhiyun  <0> - external high precision timer reference clock (TSEC_TMR_CLK
58*4882a593Smuzhiyun        input is used for this purpose);
59*4882a593Smuzhiyun  <1> - eTSEC system clock;
60*4882a593Smuzhiyun  <2> - eTSEC1 transmit clock;
61*4882a593Smuzhiyun  <3> - RTC clock input.
62*4882a593Smuzhiyun
63*4882a593Smuzhiyun  For DPAA FMan,
64*4882a593Smuzhiyun  <0> - external high precision timer reference clock (TMR_1588_CLK)
65*4882a593Smuzhiyun  <1> - MAC system clock (1/2 FMan clock)
66*4882a593Smuzhiyun  <2> - reserved
67*4882a593Smuzhiyun  <3> - RTC clock oscillator
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun  When this attribute is not used, the IEEE 1588 timer reference clock
70*4882a593Smuzhiyun  will use the eTSEC system clock (for Gianfar) or the MAC system
71*4882a593Smuzhiyun  clock (for DPAA).
72*4882a593Smuzhiyun
73*4882a593SmuzhiyunExample:
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75*4882a593Smuzhiyun	ptp_clock@24e00 {
76*4882a593Smuzhiyun		compatible = "fsl,etsec-ptp";
77*4882a593Smuzhiyun		reg = <0x24E00 0xB0>;
78*4882a593Smuzhiyun		interrupts = <12 0x8 13 0x8>;
79*4882a593Smuzhiyun		interrupt-parent = < &ipic >;
80*4882a593Smuzhiyun		fsl,cksel       = <1>;
81*4882a593Smuzhiyun		fsl,tclk-period = <10>;
82*4882a593Smuzhiyun		fsl,tmr-prsc    = <100>;
83*4882a593Smuzhiyun		fsl,tmr-add     = <0x999999A4>;
84*4882a593Smuzhiyun		fsl,tmr-fiper1  = <0x3B9AC9F6>;
85*4882a593Smuzhiyun		fsl,tmr-fiper2  = <0x00018696>;
86*4882a593Smuzhiyun		fsl,max-adj     = <659999998>;
87*4882a593Smuzhiyun	};
88