1*4882a593SmuzhiyunDevice tree Clock bindings for Renesas EMMA Mobile EV2 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunThis binding uses the common clock binding. 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun* SMU 6*4882a593SmuzhiyunSystem Management Unit described in user's manual R19UH0037EJ1000_SMU. 7*4882a593SmuzhiyunThis is not a clock provider, but clocks under SMU depend on it. 8*4882a593Smuzhiyun 9*4882a593SmuzhiyunRequired properties: 10*4882a593Smuzhiyun- compatible: Should be "renesas,emev2-smu" 11*4882a593Smuzhiyun- reg: Address and Size of SMU registers 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun* SMU_CLKDIV 14*4882a593SmuzhiyunFunction block with an input mux and a divider, which corresponds to 15*4882a593Smuzhiyun"Serial clock generator" in fig."Clock System Overview" of the manual, 16*4882a593Smuzhiyunand "xxx frequency division setting register" (XXXCLKDIV) registers. 17*4882a593SmuzhiyunThis makes internal (neither input nor output) clock that is provided 18*4882a593Smuzhiyunto input of xxxGCLK block. 19*4882a593Smuzhiyun 20*4882a593SmuzhiyunRequired properties: 21*4882a593Smuzhiyun- compatible: Should be "renesas,emev2-smu-clkdiv" 22*4882a593Smuzhiyun- reg: Byte offset from SMU base and Bit position in the register 23*4882a593Smuzhiyun- clocks: Parent clocks. Input clocks as described in clock-bindings.txt 24*4882a593Smuzhiyun- #clock-cells: Should be <0> 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun* SMU_GCLK 27*4882a593SmuzhiyunClock gating node shown as "Clock stop processing block" in the 28*4882a593Smuzhiyunfig."Clock System Overview" of the manual. 29*4882a593SmuzhiyunRegisters are "xxx clock gate control register" (XXXGCLKCTRL). 30*4882a593Smuzhiyun 31*4882a593SmuzhiyunRequired properties: 32*4882a593Smuzhiyun- compatible: Should be "renesas,emev2-smu-gclk" 33*4882a593Smuzhiyun- reg: Byte offset from SMU base and Bit position in the register 34*4882a593Smuzhiyun- clocks: Input clock as described in clock-bindings.txt 35*4882a593Smuzhiyun- #clock-cells: Should be <0> 36*4882a593Smuzhiyun 37*4882a593SmuzhiyunExample of provider: 38*4882a593Smuzhiyun 39*4882a593Smuzhiyunusia_u0_sclkdiv: usia_u0_sclkdiv { 40*4882a593Smuzhiyun compatible = "renesas,emev2-smu-clkdiv"; 41*4882a593Smuzhiyun reg = <0x610 0>; 42*4882a593Smuzhiyun clocks = <&pll3_fo>, <&pll4_fo>, <&pll1_fo>, <&osc1_fo>; 43*4882a593Smuzhiyun #clock-cells = <0>; 44*4882a593Smuzhiyun}; 45*4882a593Smuzhiyun 46*4882a593Smuzhiyunusia_u0_sclk: usia_u0_sclk { 47*4882a593Smuzhiyun compatible = "renesas,emev2-smu-gclk"; 48*4882a593Smuzhiyun reg = <0x4a0 1>; 49*4882a593Smuzhiyun clocks = <&usia_u0_sclkdiv>; 50*4882a593Smuzhiyun #clock-cells = <0>; 51*4882a593Smuzhiyun}; 52*4882a593Smuzhiyun 53*4882a593SmuzhiyunExample of consumer: 54*4882a593Smuzhiyun 55*4882a593Smuzhiyunserial@e1020000 { 56*4882a593Smuzhiyun compatible = "renesas,em-uart"; 57*4882a593Smuzhiyun reg = <0xe1020000 0x38>; 58*4882a593Smuzhiyun interrupts = <0 8 0>; 59*4882a593Smuzhiyun clocks = <&usia_u0_sclk>; 60*4882a593Smuzhiyun clock-names = "sclk"; 61*4882a593Smuzhiyun}; 62*4882a593Smuzhiyun 63*4882a593SmuzhiyunExample of clock-tree description: 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun This describes a clock path in the clock tree 66*4882a593Smuzhiyun c32ki -> pll3_fo -> usia_u0_sclkdiv -> usia_u0_sclk 67*4882a593Smuzhiyun 68*4882a593Smuzhiyunsmu@e0110000 { 69*4882a593Smuzhiyun compatible = "renesas,emev2-smu"; 70*4882a593Smuzhiyun reg = <0xe0110000 0x10000>; 71*4882a593Smuzhiyun #address-cells = <2>; 72*4882a593Smuzhiyun #size-cells = <0>; 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun c32ki: c32ki { 75*4882a593Smuzhiyun compatible = "fixed-clock"; 76*4882a593Smuzhiyun clock-frequency = <32768>; 77*4882a593Smuzhiyun #clock-cells = <0>; 78*4882a593Smuzhiyun }; 79*4882a593Smuzhiyun pll3_fo: pll3_fo { 80*4882a593Smuzhiyun compatible = "fixed-factor-clock"; 81*4882a593Smuzhiyun clocks = <&c32ki>; 82*4882a593Smuzhiyun clock-div = <1>; 83*4882a593Smuzhiyun clock-mult = <7000>; 84*4882a593Smuzhiyun #clock-cells = <0>; 85*4882a593Smuzhiyun }; 86*4882a593Smuzhiyun usia_u0_sclkdiv: usia_u0_sclkdiv { 87*4882a593Smuzhiyun compatible = "renesas,emev2-smu-clkdiv"; 88*4882a593Smuzhiyun reg = <0x610 0>; 89*4882a593Smuzhiyun clocks = <&pll3_fo>; 90*4882a593Smuzhiyun #clock-cells = <0>; 91*4882a593Smuzhiyun }; 92*4882a593Smuzhiyun usia_u0_sclk: usia_u0_sclk { 93*4882a593Smuzhiyun compatible = "renesas,emev2-smu-gclk"; 94*4882a593Smuzhiyun reg = <0x4a0 1>; 95*4882a593Smuzhiyun clocks = <&usia_u0_sclkdiv>; 96*4882a593Smuzhiyun #clock-cells = <0>; 97*4882a593Smuzhiyun }; 98*4882a593Smuzhiyun}; 99