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/OK3568_Linux_fs/u-boot/arch/arm/dts/
H A Dat91sam9g20.dtsi2 * at91sam9g20.dtsi - Device Tree Include file for AT91SAM9G20 family SoC
4 * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
24 compatible = "mmio-sram";
31 compatible = "atmel,at91sam9g20-i2c";
34 ssc0: ssc@fffbc000 {
35 compatible = "atmel,at91sam9rl-ssc";
39 atmel,adc-startup-time = <40>;
44 atmel,clk-input-range = <2000000 32000000>;
45 atmel,pll-clk-output-ranges = <745000000 800000000 0 0>,
56 compatible = "atmel,at91sam9g20-clk-pllb";
[all …]
H A Dat91sam9261.dtsi2 * at91sam9261.dtsi - Device Tree Include file for AT91SAM9261 SoC
4 * Copyright (C) 2013 Jean-Jacques Hiblot <jjhiblot@traphandler.com>
10 #include <dt-bindings/pinctrl/at91.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/clock/at91.h>
18 interrupt-parent = <&aic>;
37 #address-cells = <0>;
38 #size-cells = <0>;
41 compatible = "arm,arm926ej-s";
[all …]
H A Dat91sam9263.dtsi2 * at91sam9263.dtsi - Device Tree Include file for AT91SAM9263 family SoC
4 * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
10 #include <dt-bindings/pinctrl/at91.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/clock/at91.h>
18 interrupt-parent = <&aic>;
39 #address-cells = <0>;
40 #size-cells = <0>;
43 compatible = "arm,arm926ej-s";
[all …]
H A Dsama5d3.dtsi2 * sama5d3.dtsi - Device Tree Include file for SAMA5D3 family SoC
12 #include <dt-bindings/dma/at91.h>
13 #include <dt-bindings/pinctrl/at91.h>
14 #include <dt-bindings/interrupt-controller/irq.h>
15 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/clock/at91.h>
21 interrupt-parent = <&aic>;
44 #address-cells = <1>;
45 #size-cells = <0>;
48 compatible = "arm,cortex-a5";
[all …]
H A Dat91sam9rl.dtsi2 * at91sam9rl.dtsi - Device Tree Include file for AT91SAM9RL family SoC
4 * Copyright (C) 2014 Alexandre Belloni <alexandre.belloni@free-electrons.com>
10 #include <dt-bindings/pinctrl/at91.h>
11 #include <dt-bindings/clock/at91.h>
12 #include <dt-bindings/interrupt-controller/irq.h>
13 #include <dt-bindings/gpio/gpio.h>
14 #include <dt-bindings/pwm/pwm.h>
19 interrupt-parent = <&aic>;
41 #address-cells = <0>;
42 #size-cells = <0>;
[all …]
H A Dexynos5420-peach-pit.dts2 * SAMSUNG/GOOGLE Peach-Pit board device tree source
7 * SPDX-License-Identifier: GPL-2.0+
10 /dts-v1/;
12 #include <dt-bindings/clock/maxim,max77802.h>
13 #include <dt-bindings/regulator/maxim,max77802.h>
18 compatible = "google,pit-rev#", "google,pit",
22 google,bad-wake-gpios = <&gpx0 6 GPIO_ACTIVE_HIGH>;
23 hwid = "PIT TEST A-A 7848";
24 lazy-init = <1>;
35 compatible = "pwm-backlight";
[all …]
H A Dat91sam9g45.dtsi2 * at91sam9g45.dtsi - Device Tree Include file for AT91SAM9G45 family SoC
13 #include <dt-bindings/dma/at91.h>
14 #include <dt-bindings/pinctrl/at91.h>
15 #include <dt-bindings/interrupt-controller/irq.h>
16 #include <dt-bindings/gpio/gpio.h>
17 #include <dt-bindings/clock/at91.h>
22 interrupt-parent = <&aic>;
44 #address-cells = <0>;
45 #size-cells = <0>;
48 compatible = "arm,arm926ej-s";
[all …]
H A Dexynos5250-spring.dts7 * SPDX-License-Identifier: GPL-2.0
10 /dts-v1/;
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/interrupt-controller/irq.h>
13 #include <dt-bindings/input/input.h>
53 stdout-path = "serial3:115200n8";
56 board-rev {
57 compatible = "google,board-revision";
58 google,board-rev-gpios = <&gpy4 0 0>, <&gpy4 1 0>,
63 clock-frequency = <100000>;
[all …]
H A Dat91sam9260.dtsi2 * at91sam9260.dtsi - Device Tree Include file for AT91SAM9260 family SoC
6 * 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
12 #include <dt-bindings/pinctrl/at91.h>
13 #include <dt-bindings/interrupt-controller/irq.h>
14 #include <dt-bindings/gpio/gpio.h>
15 #include <dt-bindings/clock/at91.h>
20 interrupt-parent = <&aic>;
40 #address-cells = <0>;
41 #size-cells = <0>;
44 compatible = "arm,arm926ej-s";
[all …]
H A Dat91sam9n12.dtsi2 * at91sam9n12.dtsi - Device Tree include file for AT91SAM9N12 SoC
11 #include <dt-bindings/dma/at91.h>
12 #include <dt-bindings/pinctrl/at91.h>
13 #include <dt-bindings/interrupt-controller/irq.h>
14 #include <dt-bindings/gpio/gpio.h>
15 #include <dt-bindings/clock/at91.h>
20 interrupt-parent = <&aic>;
41 #address-cells = <0>;
42 #size-cells = <0>;
45 compatible = "arm,arm926ej-s";
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/phy/
H A Drenesas,usb3-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/renesas,usb3-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas R-Car generation 3 USB 3.0 PHY
10 - Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
15 - enum:
16 - renesas,r8a774a1-usb3-phy # RZ/G2M
17 - renesas,r8a774b1-usb3-phy # RZ/G2N
18 - renesas,r8a774e1-usb3-phy # RZ/G2H
[all …]
H A Dbrcm-sata-phy.txt4 - compatible: should be one or more of
5 "brcm,bcm7216-sata-phy"
6 "brcm,bcm7425-sata-phy"
7 "brcm,bcm7445-sata-phy"
8 "brcm,iproc-ns2-sata-phy"
9 "brcm,iproc-nsp-sata-phy"
10 "brcm,phy-sata3"
11 "brcm,iproc-sr-sata-phy"
12 "brcm,bcm63138-sata-phy"
13 - address-cells: should be 1
[all …]
H A Dphy-miphy28lp.txt8 - compatible : Should be "st,miphy28lp-phy".
9 - st,syscfg : Should be a phandle of the system configuration register group
12 Required nodes : A sub-node is required for each channel the controller
13 provides. Address range information including the usual
14 'reg' and 'reg-names' properties are used inside these
19 - #phy-cells : Should be 1 (See second example)
21 - PHY_TYPE_SATA
22 - PHY_TYPE_PCI
23 - PHY_TYPE_USB3
24 - reg : Address and length of the register set for the device.
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/rockchip/
H A Danalogix_dp-rockchip.c1 // SPDX-License-Identifier: GPL-2.0-or-later
6 * Author: Andy Yan <andy.yan@rock-chips.com>
7 * Yakir Yang <ykk@rock-chips.com>
8 * Jeff Chen <jeff.chen@rock-chips.com>
54 * struct rockchip_dp_chip_data - splite the grf setting of kind of chips
60 * @ssc: check if SSC is supported by source
70 bool ssc; member
109 if (!field->valid) in rockchip_grf_field_write()
112 mask = GENMASK(field->msb, field->lsb); in rockchip_grf_field_write()
113 val <<= field->lsb; in rockchip_grf_field_write()
[all …]
/OK3568_Linux_fs/kernel/drivers/spi/
H A Dspi-st-ssc4.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2008-2014 STMicroelectronics Limited
26 /* SSC registers */
34 /* SSC Control */
49 /* SSC Interrupt Enable */
55 /* SSC SPI Controller */
60 /* SSC SPI current transaction */
75 if (spi_st->words_remaining > FIFO_SIZE) in ssc_write_tx_fifo()
78 count = spi_st->words_remaining; in ssc_write_tx_fifo()
81 if (spi_st->tx_ptr) { in ssc_write_tx_fifo()
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/clock/
H A Dti,cdce925.txt6 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
15 - compatible: Shall be one of the following:
16 - "ti,cdce913": 1-PLL, 3 Outputs
17 - "ti,cdce925": 2-PLL, 5 Outputs
18 - "ti,cdce937": 3-PLL, 7 Outputs
19 - "ti,cdce949": 4-PLL, 9 Outputs
20 - reg: I2C device address.
21 - clocks: Points to a fixed parent clock that provides the input frequency.
22 - #clock-cells: From common clock bindings: Shall be 1.
25 - xtal-load-pf: Crystal load-capacitor value to fine-tune performance on a
[all …]
/OK3568_Linux_fs/kernel/drivers/phy/st/
H A Dphy-miphy28lp.c1 // SPDX-License-Identifier: GPL-2.0-only
24 #include <dt-bindings/phy/phy.h>
170 * 0: 30MHz crystal clk - 1: 100MHz ext clk routed through MiPHY1
172 * 1: 30MHz crystal clk - 0: 100MHz ext clk routed through MiPHY1
210 bool ssc; member
237 static char *PHY_TYPE_name[] = { "sata-up", "pcie-up", "", "usb3-up" };
366 void __iomem *base = miphy_phy->base; in miphy28lp_set_reset()
377 /* Bringing the MIPHY-CPU registers out of reset */ in miphy28lp_set_reset()
378 if (miphy_phy->type == PHY_TYPE_PCIE) { in miphy28lp_set_reset()
390 void __iomem *base = miphy_phy->base; in miphy28lp_pll_calibration()
[all …]
/OK3568_Linux_fs/kernel/block/
H A Dopal_proto.h1 /* SPDX-License-Identifier: GPL-2.0 */
16 * SPC-4 section
202 /* Locking state for a locking range */
263 * Opal SSC Documentation
317 * bits 6-7: reserved
349 * bits 1-6: reserved
360 * Enterprise SSC Feature
368 * bits 1-6: reserved
369 * bit 0: range crossing
399 * bits 3-7: reserved
[all …]
/OK3568_Linux_fs/kernel/sound/spi/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
21 This driver requires the Atmel SSC driver for sound sink, a
25 called snd-at73c213.
31 range 8000 50000
/OK3568_Linux_fs/kernel/drivers/phy/renesas/
H A Dphy-rcar-gen3-usb3.c1 // SPDX-License-Identifier: GPL-2.0
3 * Renesas R-Car Gen3 for USB3.0 PHY driver
65 writew(val, r->base + USB30_CLKSET1); in write_clkset1_for_usb_extal()
72 switch (r->ssc_range) { in rcar_gen3_phy_usb3_enable_ssc()
83 dev_err(&r->phy->dev, "%s: unsupported range (%x)\n", __func__, in rcar_gen3_phy_usb3_enable_ssc()
84 r->ssc_range); in rcar_gen3_phy_usb3_enable_ssc()
88 writew(val, r->base + USB30_SSC_SET); in rcar_gen3_phy_usb3_enable_ssc()
94 if (r->ssc_range) in rcar_gen3_phy_usb3_select_usb_extal()
97 r->base + USB30_CLKSET0); in rcar_gen3_phy_usb3_select_usb_extal()
98 writew(PHY_ENABLE_RESET_EN, r->base + USB30_PHY_ENABLE); in rcar_gen3_phy_usb3_select_usb_extal()
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/bridge/
H A Dparade-ps8622.c1 // SPDX-License-Identifier: GPL-2.0-only
69 struct i2c_adapter *adap = client->adapter; in ps8622_set()
73 msg.addr = client->addr + page; in ps8622_set()
81 client->addr + page, reg, val, ret); in ps8622_set()
87 struct i2c_client *cl = ps8622->client; in ps8622_send_config()
138 /* [7:5] DCO_FTRNG=+-40% */ in ps8622_send_config()
148 /* Gitune=-37% */ in ps8622_send_config()
168 /* [7:6] Right-bar GPIO output strength is 8mA */ in ps8622_send_config()
180 err = ps8622_set(cl, 0x01, 0x02, 0x80 | ps8622->max_lane_count); in ps8622_send_config()
185 err = ps8622_set(cl, 0x01, 0x21, 0x80 | ps8622->lane_count); in ps8622_send_config()
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/bridge/analogix/
H A Danalogix_dp_reg.c1 // SPDX-License-Identifier: GPL-2.0-or-later
24 if (dp->plat_data && is_rockchip(dp->plat_data->dev_type)) { in analogix_dp_write()
25 readl(dp->reg_base); in analogix_dp_write()
26 writel(val, dp->reg_base + reg); in analogix_dp_write()
29 writel(val, dp->reg_base + reg); in analogix_dp_write()
34 if (dp->plat_data && is_rockchip(dp->plat_data->dev_type)) in analogix_dp_read()
35 readl(dp->reg_base + reg); in analogix_dp_read()
37 return readl(dp->reg_base + reg); in analogix_dp_read()
66 struct video_info *video_info = &dp->video_info; in analogix_dp_set_lane_map()
69 for (i = 0; i < video_info->max_lane_count; i++) in analogix_dp_set_lane_map()
[all …]
/OK3568_Linux_fs/kernel/Documentation/scsi/
H A DFlashPoint.rst1 .. SPDX-License-Identifier: GPL-2.0
17 FREMONT, CA, -- October 8, 1996 -- Mylex Corporation has expanded Linux
33 Linux is a freely-distributed implementation of UNIX for Intel x86, Sun
35 machines. It supports a wide range of software, including the X Window
37 http://www.linux.org and http://www.ssc.com/.
55 and system boards. Through its wide range of RAID controllers and its
71 510/796-6100
78 BusLogic FlashPoint LT/BT-948 Upgrade Program
82 BusLogic FlashPoint LW/BT-958 Upgrade Program
99 customers to make sure the BT-946C/956C MultiMaster cards would still be
[all …]
/OK3568_Linux_fs/kernel/drivers/clk/tegra/
H A Dclk.h1 /* SPDX-License-Identifier: GPL-2.0-only */
9 #include <linux/clk-provider.h>
73 * struct tegra_clk_sync_source - external clock source from codec
75 * @hw: handle between common and hardware-specific interfaces
95 * struct tegra_clk_frac_div - fractional divider clock
97 * @hw: handle between common and hardware-specific interfaces
99 * @flags: hardware-specific flags
106 * TEGRA_DIVIDER_ROUND_UP - This flags indicates to round up the divider value.
107 * TEGRA_DIVIDER_FIXED - Fixed rate PLL dividers has addition override bit, this
109 * TEGRA_DIVIDER_INT - Some modules can not cope with the duty cycle when
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/msm/dsi/pll/
H A Ddsi_pll_14nm.c1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <linux/clk-provider.h>
13 * DSI PLL 14nm - clock diagram (eg: DSI0):
18 * +----+ | +----+
19 * dsi0vco_clk ---| n1 |--o--| /8 |-- dsi0pllbyte
20 * +----+ | +----+
22 * | +----+ |
23 * o---| /2 |--o--|\
24 * | +----+ | \ +----+
25 * | | |--| n2 |-- dsi0pll
[all …]

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