| /OK3568_Linux_fs/kernel/drivers/net/ethernet/ibm/emac/ |
| H A D | core.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
5 * Driver for PowerPC 4xx on-chip ethernet controller.
10 * Based on the arch/ppc version of the driver:
15 * Based on original work by
28 #include <linux/dma-mapping.h>
81 * - normal statistics (packet count, etc)
82 * - error statistics
192 /* Device-tree based phy configuration */
364 (EMAC_FTRS_POSSIBLE & dev->features & feature); in emac_has_feature()
369 * address match slots, 2) width of the registers for handling address
[all …]
|
| /OK3568_Linux_fs/kernel/tools/arch/x86/include/asm/ |
| H A D | orc_types.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
13 * The ORC_REG_* registers are base registers which are used to find other
14 * registers on the stack.
23 * The most commonly used base registers are SP and BP -- which the previous SP
24 * is usually based on -- and PREV_SP and UNDEFINED -- which the previous BP is
25 * usually based on.
27 * The rest of the base registers are needed for special cases like entry code
46 * CFI, simplified for ease of access by the in-kernel unwinder. It tells the
|
| /OK3568_Linux_fs/kernel/arch/x86/include/asm/ |
| H A D | orc_types.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
13 * The ORC_REG_* registers are base registers which are used to find other
14 * registers on the stack.
23 * The most commonly used base registers are SP and BP -- which the previous SP
24 * is usually based on -- and PREV_SP and UNDEFINED -- which the previous BP is
25 * usually based on.
27 * The rest of the base registers are needed for special cases like entry code
46 * CFI, simplified for ease of access by the in-kernel unwinder. It tells the
|
| /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/memory-controllers/ |
| H A D | nvidia,tegra20-emc.txt | 4 - name : Should be emc
5 - #address-cells : Should be 1
6 - #size-cells : Should be 0
7 - compatible : Should contain "nvidia,tegra20-emc".
8 - reg : Offset and length of the register set for the device
9 - nvidia,use-ram-code : If present, the sub-nodes will be addressed
12 irrespective of ram-code configuration.
13 - interrupts : Should contain EMC General interrupt.
14 - clocks : Should contain EMC clock.
20 memory-controller@7000f400 {
[all …]
|
| /OK3568_Linux_fs/kernel/drivers/hwtracing/coresight/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
14 a topological view of the CoreSight components based on a DT
31 modules will be called coresight-funnel and coresight-replicator.
40 trace router - ETR) or sink (embedded trace FIFO). The driver
45 module will be called coresight-tmc.
53 lookup. CATU helps TMC ETR to use a large physically non-contiguous trace
55 by looking up the provided table. CATU can also be used in pass-through
59 module will be called coresight-catu.
66 responsible for bridging the gap between the on-chip coresight
67 components and a trace for bridging the gap between the on-chip
[all …]
|
| /OK3568_Linux_fs/kernel/Documentation/virt/kvm/devices/ |
| H A D | arm-vgic-v3.rst | 1 .. SPDX-License-Identifier: GPL-2.0
9 - KVM_DEV_TYPE_ARM_VGIC_V3 ARM Generic Interrupt Controller v3.0
12 will act as the VM interrupt controller, requiring emulated user-space devices
23 KVM_VGIC_V3_ADDR_TYPE_DIST (rw, 64-bit)
28 KVM_VGIC_V3_ADDR_TYPE_REDIST (rw, 64-bit)
35 KVM_VGIC_V3_ADDR_TYPE_REDIST_REGION (rw, 64-bit)
38 bits: | 63 .... 52 | 51 .... 16 | 15 - 12 |11 - 0
41 - index encodes the unique redistributor region index
42 - flags: reserved for future use, currently 0
43 - base field encodes bits [51:16] of the guest physical base address
[all …]
|
| /OK3568_Linux_fs/kernel/drivers/net/can/sja1000/ |
| H A D | plx_pci.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2008-2010 Pavel Cheblakov <P.B.Cheblakov@inp.nsk.su>
7 * Copyright (C) 2008 Markus Plessing <plessing@ems-wuensche.com>
8 * Copyright (C) 2008 Sebastian Haas <haas@ems-wuensche.com>
26 MODULE_DESCRIPTION("Socket-CAN driver for PLX90xx PCI-bridge cards with "
28 MODULE_SUPPORTED_DEVICE("Adlink PCI-7841/cPCI-7841, "
29 "Adlink PCI-7841/cPCI-7841 SE, "
30 "Marathon CAN-bus-PCI, "
31 "Marathon CAN-bus-PCIe, "
33 "esd CAN-PCI/CPCI/PCI104/200, "
[all …]
|
| /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/arm/bcm/ |
| H A D | brcm,brcmstb.txt | 2 -----------------------------------------------
3 Boards with Broadcom Brahma15 ARM-based BCMxxxx (generally BCM7xxx variants)
7 - compatible: "brcm,bcm<chip_id>", "brcm,brcmstb"
11 #address-cells = <2>;
12 #size-cells = <2>;
16 Further, syscon nodes that map platform-specific registers used for general
19 - compatible: "brcm,bcm<chip_id>-sun-top-ctrl", "syscon"
20 - compatible: "brcm,bcm<chip_id>-cpu-biu-ctrl",
21 "brcm,brcmstb-cpu-biu-ctrl",
23 - compatible: "brcm,bcm<chip_id>-hif-continuation", "syscon"
[all …]
|
| /OK3568_Linux_fs/kernel/Documentation/trace/coresight/ |
| H A D | coresight-cpu-debug.rst | 9 ------------
11 Coresight CPU debug module is defined in ARMv8-a architecture reference manual
13 debug module and it is mainly used for two modes: self-hosted debug and
16 explore debugging method which rely on self-hosted debug mode, this document
19 The debug module provides sample-based profiling extension, which can be used
21 every CPU has one dedicated debug module to be connected. Based on self-hosted
22 debug mechanism, Linux kernel can access these related registers from mmio
24 will dump related registers for every CPU; finally this is good for assistant
29 --------------
31 - During driver registration, it uses EDDEVID and EDDEVID1 - two device ID
[all …]
|
| /OK3568_Linux_fs/kernel/drivers/gpu/drm/bridge/ |
| H A D | tc358762.c | 1 // SPDX-License-Identifier: GPL-2.0
5 * Based on tc358764.c by
9 * Based on rpi_touchscreen.c by
29 /* PPI layer registers */
38 /* DSI layer registers */
39 #define DSI_STARTDSI 0x0204 /* START control bit of DSI-TX */
43 /* LCDC/DPI Host Registers */
46 /* SPI Master Registers */
50 /* System Controller Registers */
53 /* System registers */
[all …]
|
| /OK3568_Linux_fs/kernel/tools/power/cpupower/man/ |
| H A D | cpupower-monitor.1 | 1 .TH CPUPOWER\-MONITOR "1" "22/02/2011" "" "cpupower Manual"
3 cpupower\-monitor \- Report processor frequency and idle statistics
7 .RB "\-l"
10 .RB [ -c ] [ "\-m <mon1>," [ "<mon2>,..." ] ]
11 .RB [ "\-i seconds" ]
14 .RB [ -c ][ "\-m <mon1>," [ "<mon2>,..." ] ]
18 \fBcpupower-monitor \fP reports processor topology, frequency and idle power
22 \fBcpupower-monitor \fP implements independent processor sleep state and
24 directly reading out hardware registers. Use \-l to get an overview which are
29 \-l
[all …]
|
| /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/pci/ |
| H A D | kirin-pcie.txt | 3 Kirin PCIe host controller is based on the Synopsys DesignWare PCI core.
6 Documentation/devicetree/bindings/pci/designware-pcie.txt.
11 - compatible:
12 "hisilicon,kirin960-pcie" for PCIe of Kirin960 SoC
13 - reg: Should contain rc_dbi, apb, phy, config registers location and length.
14 - reg-names: Must include the following entries:
15 "dbi": controller configuration registers;
18 "config": PCIe configuration space registers.
19 - reset-gpios: The GPIO to generate PCIe PERST# assert and deassert signal.
23 Example based on kirin960:
[all …]
|
| H A D | pci-keystone.txt | 3 Keystone PCI host Controller is based on the Synopsys DesignWare PCI
6 Documentation/devicetree/bindings/pci/designware-pcie.txt
8 Please refer to Documentation/devicetree/bindings/pci/designware-pcie.txt
12 Required Properties:-
14 compatibility: Should be "ti,keystone-pcie" for RC on Keystone2 SoC
15 Should be "ti,am654-pcie-rc" for RC on AM654x SoC
16 reg: Three register ranges as listed in the reg-names property
17 reg-names: "dbics" for the DesignWare PCIe registers, "app" for the
18 TI specific application registers, "config" for the
22 interrupt-cells: should be set to 1
[all …]
|
| /OK3568_Linux_fs/kernel/Documentation/driver-api/soundwire/ |
| H A D | summary.rst | 10 SoundWire is a 2-pin multi-drop interface with data and clock line. It
15 commands over a single two-pin interface.
23 (4) Device status monitoring, including interrupt-style alerts to the Master.
38 +---------------+ +---------------+
40 | Master |-------+-------------------------------| Slave |
42 | |-------|-------+-----------------------| |
43 +---------------+ | | +---------------+
47 +--+-------+--+
52 +-------------+
64 3rd-party vendors to enable implementation-defined functionality while
[all …]
|
| /OK3568_Linux_fs/kernel/drivers/gpu/arm/midgard/backend/gpu/ |
| H A D | mali_kbase_gpu.c | 3 * (C) COPYRIGHT 2014-2016 ARM Limited. All rights reserved.
12 * Boston, MA 02110-1301, USA.
20 * Register-based HW access backend APIs
37 /* Ensure we can access the GPU registers */ in kbase_backend_early_init()
40 /* Find out GPU properties based on the GPU feature registers */ in kbase_backend_early_init()
43 /* We're done accessing the GPU registers for now. */ in kbase_backend_early_init()
86 dev_err(kbdev->dev, "Interrupt assigment check failed.\n"); in kbase_backend_late_init()
87 err = -EINVAL; in kbase_backend_late_init()
97 init_waitqueue_head(&kbdev->hwaccess.backend.reset_wait); in kbase_backend_late_init()
|
| /OK3568_Linux_fs/kernel/drivers/staging/mt7621-pci/ |
| H A D | mediatek,mt7621-pci.txt | 4 - compatible: "mediatek,mt7621-pci"
5 - device_type: Must be "pci"
6 - reg: Base addresses and lengths of the PCIe subsys and root ports.
7 - bus-range: Range of bus numbers associated with this controller.
8 - #address-cells: Address representation for root ports (must be 3)
9 - pinctrl-names : The pin control state names.
10 - pinctrl-0: The "default" pinctrl state.
11 - #size-cells: Size representation for root ports (must be 2)
12 - ranges: Ranges for the PCI memory and I/O regions.
13 - #interrupt-cells: Must be 1
[all …]
|
| /OK3568_Linux_fs/kernel/include/video/ |
| H A D | cirrus.h | 2 * drivers/video/clgenfb.h - Cirrus Logic chipset constants
8 * Based on retz3fb.c and clgen.c:
14 * Format this code with GNU indent '-kr -i8 -pcs' options.
27 /* OLD COMMENT: for other CL-GD542x/543x based boards.. */
29 /*** External/General Registers ***/
34 /*** VGA Sequencer Registers ***/
35 /* the following are from the "extension registers" group */
50 #define CL_SEQR14 0x14 /* Scratch Pad 2 (CL-GD5426/'28 Only) (do not access!) */
51 #define CL_SEQR15 0x15 /* Scratch Pad 3 (CL-GD5426/'28 Only) (do not access!) */
52 #define CL_SEQR16 0x16 /* Performance Tuning (CL-GD5424/'26/'28 Only) */
[all …]
|
| /OK3568_Linux_fs/kernel/sound/soc/intel/skylake/ |
| H A D | skl-sst-cldma.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
22 /* Intel HD Audio Code Loader DMA Registers */
26 /* Stream Registers */
39 /* CL: Software Position Based FIFO Capability Registers */
155 * Code Loader - Software Position Based FIFO
156 * Capability Registers x Software Position Based FIFO Header
213 * skl_cl_dev - holds information for code loader dma transfer
|
| /OK3568_Linux_fs/kernel/drivers/net/mdio/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
20 loadable module or built-in.
44 tristate "APM X-Gene SoC MDIO bus controller"
48 APM X-Gene SoC's.
57 third revision of the ASPEED MDIO register interface - the first two
94 tristate "GPIO lib-based bitbanged MDIO buses"
98 Supports GPIO lib-based MDIO busses.
101 will be called mdio-gpio.
114 Support I2C based PHYs. This provides a MDIO bus bridged
160 IPQ40xx series Soc-s.
[all …]
|
| /OK3568_Linux_fs/u-boot/drivers/ddr/fsl/ |
| H A D | Kconfig | 5 PowerPC- based SoCs (such as mpc83xx, mpc85xx, mpc86xx) and ARM-
6 based Layerscape SoCs (such as ls2080a).
16 Access DDR registers in big-endian
21 Access DDR registers in little-endian
|
| /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/powerpc/fsl/ |
| H A D | dcsr.txt | 21 - compatible
24 Definition: Must include "fsl,dcsr" and "simple-bus".
25 The DCSR space exists in the memory-mapped bus.
27 - #address-cells
33 - #size-cells
40 - ranges
42 Value type: <prop-encoded-array>
48 #address-cells = <1>;
49 #size-cells = <1>;
50 compatible = "fsl,dcsr", "simple-bus";
[all …]
|
| /OK3568_Linux_fs/kernel/Documentation/networking/dsa/ |
| H A D | dsa.rst | 22 An Ethernet switch is typically comprised of multiple front-panel ports, and one
27 gateways, or even top-of-the rack switches. This host Ethernet controller will
36 For each front-panel port, DSA will create specialized network devices which are
37 used as controlling and data-flowing endpoints for use by the Linux networking
46 - what port is this frame coming from
47 - what was the reason why this frame got forwarded
48 - how to send CPU originated traffic to specific ports
52 on Port-based VLAN IDs).
57 - the "cpu" port is the Ethernet switch facing side of the management
61 - the "dsa" port(s) are just conduits between two or more switches, and as such
[all …]
|
| /OK3568_Linux_fs/kernel/drivers/media/usb/gspca/ |
| H A D | se401.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
7 * Based on the v4l1 se401 driver which is:
34 /* Hyundai hv7131b registers
36 /* Mode registers: */
40 /* Frame registers: */
49 /* Timing registers: */
58 /* Adjust Registers: */
65 /* Offset Registers: */
69 /* REset level statistics registers: */
75 /* se401 registers */
|
| /OK3568_Linux_fs/kernel/Documentation/power/ |
| H A D | pci.rst | 8 management. Based on previous work by Patrick Mochel <mochel@transmeta.com>
13 power management refer to Documentation/driver-api/pm/devices.rst and
27 1.1. Native and Platform-Based Power Management
28 -----------------------------------------------
31 devices into states in which they draw less power (low-power states) at the
34 Usually, a device is put into a low-power state when it is underutilized or
36 again, it has to be put back into the "fully functional" state (full-power
41 PCI devices may be put into low-power states in two ways, by using the device
46 specific value into one of its standard configuration registers. The second
53 to put the device that sent it into the full-power state. However, the PCI Bus
[all …]
|
| /OK3568_Linux_fs/kernel/Documentation/sh/ |
| H A D | register-banks.rst | 1 .. SPDX-License-Identifier: GPL-2.0
8 ------------
10 The SH-3 and SH-4 CPU families traditionally include a single partial register
12 may have more full-featured banking or simply no such capabilities at all.
15 -------------
17 In the case of this type of banking, banked registers are mapped directly to
19 can still be used to reference the banked registers (as r0_bank ... r7_bank)
21 in mind when writing code that utilizes these banked registers, for obvious
23 be used rather effectively as scratch registers by the kernel.
25 Presently the kernel uses several of these registers.
[all …]
|