1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright (C) 2020 Marek Vasut <marex@denx.de>
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Based on tc358764.c by
6*4882a593Smuzhiyun * Andrzej Hajda <a.hajda@samsung.com>
7*4882a593Smuzhiyun * Maciej Purski <m.purski@samsung.com>
8*4882a593Smuzhiyun *
9*4882a593Smuzhiyun * Based on rpi_touchscreen.c by
10*4882a593Smuzhiyun * Eric Anholt <eric@anholt.net>
11*4882a593Smuzhiyun */
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun #include <linux/delay.h>
14*4882a593Smuzhiyun #include <linux/module.h>
15*4882a593Smuzhiyun #include <linux/of_graph.h>
16*4882a593Smuzhiyun #include <linux/regulator/consumer.h>
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun #include <video/mipi_display.h>
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun #include <drm/drm_atomic_helper.h>
21*4882a593Smuzhiyun #include <drm/drm_crtc.h>
22*4882a593Smuzhiyun #include <drm/drm_fb_helper.h>
23*4882a593Smuzhiyun #include <drm/drm_mipi_dsi.h>
24*4882a593Smuzhiyun #include <drm/drm_of.h>
25*4882a593Smuzhiyun #include <drm/drm_panel.h>
26*4882a593Smuzhiyun #include <drm/drm_print.h>
27*4882a593Smuzhiyun #include <drm/drm_probe_helper.h>
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun /* PPI layer registers */
30*4882a593Smuzhiyun #define PPI_STARTPPI 0x0104 /* START control bit */
31*4882a593Smuzhiyun #define PPI_LPTXTIMECNT 0x0114 /* LPTX timing signal */
32*4882a593Smuzhiyun #define PPI_D0S_ATMR 0x0144
33*4882a593Smuzhiyun #define PPI_D1S_ATMR 0x0148
34*4882a593Smuzhiyun #define PPI_D0S_CLRSIPOCOUNT 0x0164 /* Assertion timer for Lane 0 */
35*4882a593Smuzhiyun #define PPI_D1S_CLRSIPOCOUNT 0x0168 /* Assertion timer for Lane 1 */
36*4882a593Smuzhiyun #define PPI_START_FUNCTION 1
37*4882a593Smuzhiyun
38*4882a593Smuzhiyun /* DSI layer registers */
39*4882a593Smuzhiyun #define DSI_STARTDSI 0x0204 /* START control bit of DSI-TX */
40*4882a593Smuzhiyun #define DSI_LANEENABLE 0x0210 /* Enables each lane */
41*4882a593Smuzhiyun #define DSI_RX_START 1
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun /* LCDC/DPI Host Registers */
44*4882a593Smuzhiyun #define LCDCTRL 0x0420
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun /* SPI Master Registers */
47*4882a593Smuzhiyun #define SPICMR 0x0450
48*4882a593Smuzhiyun #define SPITCR 0x0454
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun /* System Controller Registers */
51*4882a593Smuzhiyun #define SYSCTRL 0x0464
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun /* System registers */
54*4882a593Smuzhiyun #define LPX_PERIOD 3
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun /* Lane enable PPI and DSI register bits */
57*4882a593Smuzhiyun #define LANEENABLE_CLEN BIT(0)
58*4882a593Smuzhiyun #define LANEENABLE_L0EN BIT(1)
59*4882a593Smuzhiyun #define LANEENABLE_L1EN BIT(2)
60*4882a593Smuzhiyun
61*4882a593Smuzhiyun struct tc358762 {
62*4882a593Smuzhiyun struct device *dev;
63*4882a593Smuzhiyun struct drm_bridge bridge;
64*4882a593Smuzhiyun struct drm_connector connector;
65*4882a593Smuzhiyun struct regulator *regulator;
66*4882a593Smuzhiyun struct drm_bridge *panel_bridge;
67*4882a593Smuzhiyun bool pre_enabled;
68*4882a593Smuzhiyun int error;
69*4882a593Smuzhiyun };
70*4882a593Smuzhiyun
tc358762_clear_error(struct tc358762 * ctx)71*4882a593Smuzhiyun static int tc358762_clear_error(struct tc358762 *ctx)
72*4882a593Smuzhiyun {
73*4882a593Smuzhiyun int ret = ctx->error;
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun ctx->error = 0;
76*4882a593Smuzhiyun return ret;
77*4882a593Smuzhiyun }
78*4882a593Smuzhiyun
tc358762_write(struct tc358762 * ctx,u16 addr,u32 val)79*4882a593Smuzhiyun static void tc358762_write(struct tc358762 *ctx, u16 addr, u32 val)
80*4882a593Smuzhiyun {
81*4882a593Smuzhiyun struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
82*4882a593Smuzhiyun ssize_t ret;
83*4882a593Smuzhiyun u8 data[6];
84*4882a593Smuzhiyun
85*4882a593Smuzhiyun if (ctx->error)
86*4882a593Smuzhiyun return;
87*4882a593Smuzhiyun
88*4882a593Smuzhiyun data[0] = addr;
89*4882a593Smuzhiyun data[1] = addr >> 8;
90*4882a593Smuzhiyun data[2] = val;
91*4882a593Smuzhiyun data[3] = val >> 8;
92*4882a593Smuzhiyun data[4] = val >> 16;
93*4882a593Smuzhiyun data[5] = val >> 24;
94*4882a593Smuzhiyun
95*4882a593Smuzhiyun ret = mipi_dsi_generic_write(dsi, data, sizeof(data));
96*4882a593Smuzhiyun if (ret < 0)
97*4882a593Smuzhiyun ctx->error = ret;
98*4882a593Smuzhiyun }
99*4882a593Smuzhiyun
bridge_to_tc358762(struct drm_bridge * bridge)100*4882a593Smuzhiyun static inline struct tc358762 *bridge_to_tc358762(struct drm_bridge *bridge)
101*4882a593Smuzhiyun {
102*4882a593Smuzhiyun return container_of(bridge, struct tc358762, bridge);
103*4882a593Smuzhiyun }
104*4882a593Smuzhiyun
tc358762_init(struct tc358762 * ctx)105*4882a593Smuzhiyun static int tc358762_init(struct tc358762 *ctx)
106*4882a593Smuzhiyun {
107*4882a593Smuzhiyun tc358762_write(ctx, DSI_LANEENABLE,
108*4882a593Smuzhiyun LANEENABLE_L0EN | LANEENABLE_CLEN);
109*4882a593Smuzhiyun tc358762_write(ctx, PPI_D0S_CLRSIPOCOUNT, 5);
110*4882a593Smuzhiyun tc358762_write(ctx, PPI_D1S_CLRSIPOCOUNT, 5);
111*4882a593Smuzhiyun tc358762_write(ctx, PPI_D0S_ATMR, 0);
112*4882a593Smuzhiyun tc358762_write(ctx, PPI_D1S_ATMR, 0);
113*4882a593Smuzhiyun tc358762_write(ctx, PPI_LPTXTIMECNT, LPX_PERIOD);
114*4882a593Smuzhiyun
115*4882a593Smuzhiyun tc358762_write(ctx, SPICMR, 0x00);
116*4882a593Smuzhiyun tc358762_write(ctx, LCDCTRL, 0x00100150);
117*4882a593Smuzhiyun tc358762_write(ctx, SYSCTRL, 0x040f);
118*4882a593Smuzhiyun msleep(100);
119*4882a593Smuzhiyun
120*4882a593Smuzhiyun tc358762_write(ctx, PPI_STARTPPI, PPI_START_FUNCTION);
121*4882a593Smuzhiyun tc358762_write(ctx, DSI_STARTDSI, DSI_RX_START);
122*4882a593Smuzhiyun
123*4882a593Smuzhiyun msleep(100);
124*4882a593Smuzhiyun
125*4882a593Smuzhiyun return tc358762_clear_error(ctx);
126*4882a593Smuzhiyun }
127*4882a593Smuzhiyun
tc358762_post_disable(struct drm_bridge * bridge)128*4882a593Smuzhiyun static void tc358762_post_disable(struct drm_bridge *bridge)
129*4882a593Smuzhiyun {
130*4882a593Smuzhiyun struct tc358762 *ctx = bridge_to_tc358762(bridge);
131*4882a593Smuzhiyun int ret;
132*4882a593Smuzhiyun
133*4882a593Smuzhiyun /*
134*4882a593Smuzhiyun * The post_disable hook might be called multiple times.
135*4882a593Smuzhiyun * We want to avoid regulator imbalance below.
136*4882a593Smuzhiyun */
137*4882a593Smuzhiyun if (!ctx->pre_enabled)
138*4882a593Smuzhiyun return;
139*4882a593Smuzhiyun
140*4882a593Smuzhiyun ctx->pre_enabled = false;
141*4882a593Smuzhiyun
142*4882a593Smuzhiyun ret = regulator_disable(ctx->regulator);
143*4882a593Smuzhiyun if (ret < 0)
144*4882a593Smuzhiyun dev_err(ctx->dev, "error disabling regulators (%d)\n", ret);
145*4882a593Smuzhiyun }
146*4882a593Smuzhiyun
tc358762_pre_enable(struct drm_bridge * bridge)147*4882a593Smuzhiyun static void tc358762_pre_enable(struct drm_bridge *bridge)
148*4882a593Smuzhiyun {
149*4882a593Smuzhiyun struct tc358762 *ctx = bridge_to_tc358762(bridge);
150*4882a593Smuzhiyun int ret;
151*4882a593Smuzhiyun
152*4882a593Smuzhiyun ret = regulator_enable(ctx->regulator);
153*4882a593Smuzhiyun if (ret < 0)
154*4882a593Smuzhiyun dev_err(ctx->dev, "error enabling regulators (%d)\n", ret);
155*4882a593Smuzhiyun
156*4882a593Smuzhiyun ret = tc358762_init(ctx);
157*4882a593Smuzhiyun if (ret < 0)
158*4882a593Smuzhiyun dev_err(ctx->dev, "error initializing bridge (%d)\n", ret);
159*4882a593Smuzhiyun
160*4882a593Smuzhiyun ctx->pre_enabled = true;
161*4882a593Smuzhiyun }
162*4882a593Smuzhiyun
tc358762_attach(struct drm_bridge * bridge,enum drm_bridge_attach_flags flags)163*4882a593Smuzhiyun static int tc358762_attach(struct drm_bridge *bridge,
164*4882a593Smuzhiyun enum drm_bridge_attach_flags flags)
165*4882a593Smuzhiyun {
166*4882a593Smuzhiyun struct tc358762 *ctx = bridge_to_tc358762(bridge);
167*4882a593Smuzhiyun
168*4882a593Smuzhiyun return drm_bridge_attach(bridge->encoder, ctx->panel_bridge,
169*4882a593Smuzhiyun bridge, flags);
170*4882a593Smuzhiyun }
171*4882a593Smuzhiyun
172*4882a593Smuzhiyun static const struct drm_bridge_funcs tc358762_bridge_funcs = {
173*4882a593Smuzhiyun .post_disable = tc358762_post_disable,
174*4882a593Smuzhiyun .pre_enable = tc358762_pre_enable,
175*4882a593Smuzhiyun .attach = tc358762_attach,
176*4882a593Smuzhiyun };
177*4882a593Smuzhiyun
tc358762_parse_dt(struct tc358762 * ctx)178*4882a593Smuzhiyun static int tc358762_parse_dt(struct tc358762 *ctx)
179*4882a593Smuzhiyun {
180*4882a593Smuzhiyun struct drm_bridge *panel_bridge;
181*4882a593Smuzhiyun struct device *dev = ctx->dev;
182*4882a593Smuzhiyun struct drm_panel *panel;
183*4882a593Smuzhiyun int ret;
184*4882a593Smuzhiyun
185*4882a593Smuzhiyun ret = drm_of_find_panel_or_bridge(dev->of_node, 1, 0, &panel, NULL);
186*4882a593Smuzhiyun if (ret)
187*4882a593Smuzhiyun return ret;
188*4882a593Smuzhiyun
189*4882a593Smuzhiyun panel_bridge = devm_drm_panel_bridge_add(dev, panel);
190*4882a593Smuzhiyun
191*4882a593Smuzhiyun if (IS_ERR(panel_bridge))
192*4882a593Smuzhiyun return PTR_ERR(panel_bridge);
193*4882a593Smuzhiyun
194*4882a593Smuzhiyun ctx->panel_bridge = panel_bridge;
195*4882a593Smuzhiyun
196*4882a593Smuzhiyun return 0;
197*4882a593Smuzhiyun }
198*4882a593Smuzhiyun
tc358762_configure_regulators(struct tc358762 * ctx)199*4882a593Smuzhiyun static int tc358762_configure_regulators(struct tc358762 *ctx)
200*4882a593Smuzhiyun {
201*4882a593Smuzhiyun ctx->regulator = devm_regulator_get(ctx->dev, "vddc");
202*4882a593Smuzhiyun if (IS_ERR(ctx->regulator))
203*4882a593Smuzhiyun return PTR_ERR(ctx->regulator);
204*4882a593Smuzhiyun
205*4882a593Smuzhiyun return 0;
206*4882a593Smuzhiyun }
207*4882a593Smuzhiyun
tc358762_probe(struct mipi_dsi_device * dsi)208*4882a593Smuzhiyun static int tc358762_probe(struct mipi_dsi_device *dsi)
209*4882a593Smuzhiyun {
210*4882a593Smuzhiyun struct device *dev = &dsi->dev;
211*4882a593Smuzhiyun struct tc358762 *ctx;
212*4882a593Smuzhiyun int ret;
213*4882a593Smuzhiyun
214*4882a593Smuzhiyun ctx = devm_kzalloc(dev, sizeof(struct tc358762), GFP_KERNEL);
215*4882a593Smuzhiyun if (!ctx)
216*4882a593Smuzhiyun return -ENOMEM;
217*4882a593Smuzhiyun
218*4882a593Smuzhiyun mipi_dsi_set_drvdata(dsi, ctx);
219*4882a593Smuzhiyun
220*4882a593Smuzhiyun ctx->dev = dev;
221*4882a593Smuzhiyun ctx->pre_enabled = false;
222*4882a593Smuzhiyun
223*4882a593Smuzhiyun /* TODO: Find out how to get dual-lane mode working */
224*4882a593Smuzhiyun dsi->lanes = 1;
225*4882a593Smuzhiyun dsi->format = MIPI_DSI_FMT_RGB888;
226*4882a593Smuzhiyun dsi->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
227*4882a593Smuzhiyun MIPI_DSI_MODE_LPM;
228*4882a593Smuzhiyun
229*4882a593Smuzhiyun ret = tc358762_parse_dt(ctx);
230*4882a593Smuzhiyun if (ret < 0)
231*4882a593Smuzhiyun return ret;
232*4882a593Smuzhiyun
233*4882a593Smuzhiyun ret = tc358762_configure_regulators(ctx);
234*4882a593Smuzhiyun if (ret < 0)
235*4882a593Smuzhiyun return ret;
236*4882a593Smuzhiyun
237*4882a593Smuzhiyun ctx->bridge.funcs = &tc358762_bridge_funcs;
238*4882a593Smuzhiyun ctx->bridge.type = DRM_MODE_CONNECTOR_DPI;
239*4882a593Smuzhiyun ctx->bridge.of_node = dev->of_node;
240*4882a593Smuzhiyun
241*4882a593Smuzhiyun drm_bridge_add(&ctx->bridge);
242*4882a593Smuzhiyun
243*4882a593Smuzhiyun ret = mipi_dsi_attach(dsi);
244*4882a593Smuzhiyun if (ret < 0) {
245*4882a593Smuzhiyun drm_bridge_remove(&ctx->bridge);
246*4882a593Smuzhiyun dev_err(dev, "failed to attach dsi\n");
247*4882a593Smuzhiyun }
248*4882a593Smuzhiyun
249*4882a593Smuzhiyun return ret;
250*4882a593Smuzhiyun }
251*4882a593Smuzhiyun
tc358762_remove(struct mipi_dsi_device * dsi)252*4882a593Smuzhiyun static int tc358762_remove(struct mipi_dsi_device *dsi)
253*4882a593Smuzhiyun {
254*4882a593Smuzhiyun struct tc358762 *ctx = mipi_dsi_get_drvdata(dsi);
255*4882a593Smuzhiyun
256*4882a593Smuzhiyun mipi_dsi_detach(dsi);
257*4882a593Smuzhiyun drm_bridge_remove(&ctx->bridge);
258*4882a593Smuzhiyun
259*4882a593Smuzhiyun return 0;
260*4882a593Smuzhiyun }
261*4882a593Smuzhiyun
262*4882a593Smuzhiyun static const struct of_device_id tc358762_of_match[] = {
263*4882a593Smuzhiyun { .compatible = "toshiba,tc358762" },
264*4882a593Smuzhiyun { }
265*4882a593Smuzhiyun };
266*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, tc358762_of_match);
267*4882a593Smuzhiyun
268*4882a593Smuzhiyun static struct mipi_dsi_driver tc358762_driver = {
269*4882a593Smuzhiyun .probe = tc358762_probe,
270*4882a593Smuzhiyun .remove = tc358762_remove,
271*4882a593Smuzhiyun .driver = {
272*4882a593Smuzhiyun .name = "tc358762",
273*4882a593Smuzhiyun .of_match_table = tc358762_of_match,
274*4882a593Smuzhiyun },
275*4882a593Smuzhiyun };
276*4882a593Smuzhiyun module_mipi_dsi_driver(tc358762_driver);
277*4882a593Smuzhiyun
278*4882a593Smuzhiyun MODULE_AUTHOR("Marek Vasut <marex@denx.de>");
279*4882a593Smuzhiyun MODULE_DESCRIPTION("MIPI-DSI based Driver for TC358762 DSI/DPI Bridge");
280*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
281