Lines Matching +full:registers +full:- +full:based

1 .. SPDX-License-Identifier: GPL-2.0
8 ------------
10 The SH-3 and SH-4 CPU families traditionally include a single partial register
12 may have more full-featured banking or simply no such capabilities at all.
15 -------------
17 In the case of this type of banking, banked registers are mapped directly to
19 can still be used to reference the banked registers (as r0_bank ... r7_bank)
21 in mind when writing code that utilizes these banked registers, for obvious
23 be used rather effectively as scratch registers by the kernel.
25 Presently the kernel uses several of these registers.
27 	- r0_bank, r1_bank (referenced as k0 and k1, used for scratch
28 	  registers when doing exception handling).
30 	- r2_bank (used to track the EXPEVT/INTEVT code)
32 		- Used by do_IRQ() and friends for doing irq mapping based off
35 	- r6_bank (global interrupt mask)
37 		- The SR.IMASK interrupt handler makes use of this to set the
40 	- r7_bank (current)