1*4882a593SmuzhiyunHiSilicon Kirin SoCs PCIe host DT description 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunKirin PCIe host controller is based on the Synopsys DesignWare PCI core. 4*4882a593SmuzhiyunIt shares common functions with the PCIe DesignWare core driver and 5*4882a593Smuzhiyuninherits common properties defined in 6*4882a593SmuzhiyunDocumentation/devicetree/bindings/pci/designware-pcie.txt. 7*4882a593Smuzhiyun 8*4882a593SmuzhiyunAdditional properties are described here: 9*4882a593Smuzhiyun 10*4882a593SmuzhiyunRequired properties 11*4882a593Smuzhiyun- compatible: 12*4882a593Smuzhiyun "hisilicon,kirin960-pcie" for PCIe of Kirin960 SoC 13*4882a593Smuzhiyun- reg: Should contain rc_dbi, apb, phy, config registers location and length. 14*4882a593Smuzhiyun- reg-names: Must include the following entries: 15*4882a593Smuzhiyun "dbi": controller configuration registers; 16*4882a593Smuzhiyun "apb": apb Ctrl register defined by Kirin; 17*4882a593Smuzhiyun "phy": apb PHY register defined by Kirin; 18*4882a593Smuzhiyun "config": PCIe configuration space registers. 19*4882a593Smuzhiyun- reset-gpios: The GPIO to generate PCIe PERST# assert and deassert signal. 20*4882a593Smuzhiyun 21*4882a593SmuzhiyunOptional properties: 22*4882a593Smuzhiyun 23*4882a593SmuzhiyunExample based on kirin960: 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun pcie@f4000000 { 26*4882a593Smuzhiyun compatible = "hisilicon,kirin-pcie"; 27*4882a593Smuzhiyun reg = <0x0 0xf4000000 0x0 0x1000>, <0x0 0xff3fe000 0x0 0x1000>, 28*4882a593Smuzhiyun <0x0 0xf3f20000 0x0 0x40000>, <0x0 0xF4000000 0 0x2000>; 29*4882a593Smuzhiyun reg-names = "dbi","apb","phy", "config"; 30*4882a593Smuzhiyun bus-range = <0x0 0x1>; 31*4882a593Smuzhiyun #address-cells = <3>; 32*4882a593Smuzhiyun #size-cells = <2>; 33*4882a593Smuzhiyun device_type = "pci"; 34*4882a593Smuzhiyun ranges = <0x02000000 0x0 0x00000000 0x0 0xf5000000 0x0 0x2000000>; 35*4882a593Smuzhiyun num-lanes = <1>; 36*4882a593Smuzhiyun #interrupt-cells = <1>; 37*4882a593Smuzhiyun interrupt-map-mask = <0xf800 0 0 7>; 38*4882a593Smuzhiyun interrupt-map = <0x0 0 0 1 &gic 0 0 0 282 4>, 39*4882a593Smuzhiyun <0x0 0 0 2 &gic 0 0 0 283 4>, 40*4882a593Smuzhiyun <0x0 0 0 3 &gic 0 0 0 284 4>, 41*4882a593Smuzhiyun <0x0 0 0 4 &gic 0 0 0 285 4>; 42*4882a593Smuzhiyun clocks = <&crg_ctrl HI3660_PCIEPHY_REF>, 43*4882a593Smuzhiyun <&crg_ctrl HI3660_CLK_GATE_PCIEAUX>, 44*4882a593Smuzhiyun <&crg_ctrl HI3660_PCLK_GATE_PCIE_PHY>, 45*4882a593Smuzhiyun <&crg_ctrl HI3660_PCLK_GATE_PCIE_SYS>, 46*4882a593Smuzhiyun <&crg_ctrl HI3660_ACLK_GATE_PCIE>; 47*4882a593Smuzhiyun clock-names = "pcie_phy_ref", "pcie_aux", 48*4882a593Smuzhiyun "pcie_apb_phy", "pcie_apb_sys", "pcie_aclk"; 49*4882a593Smuzhiyun reset-gpios = <&gpio11 1 0 >; 50*4882a593Smuzhiyun }; 51