1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * GSPCA Endpoints (formerly known as AOX) se401 USB Camera sub Driver 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2011 Hans de Goede <hdegoede@redhat.com> 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * Based on the v4l1 se401 driver which is: 8*4882a593Smuzhiyun * 9*4882a593Smuzhiyun * Copyright (c) 2000 Jeroen B. Vreeken (pe1rxq@amsat.org) 10*4882a593Smuzhiyun */ 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #define SE401_REQ_GET_CAMERA_DESCRIPTOR 0x06 13*4882a593Smuzhiyun #define SE401_REQ_START_CONTINUOUS_CAPTURE 0x41 14*4882a593Smuzhiyun #define SE401_REQ_STOP_CONTINUOUS_CAPTURE 0x42 15*4882a593Smuzhiyun #define SE401_REQ_CAPTURE_FRAME 0x43 16*4882a593Smuzhiyun #define SE401_REQ_GET_BRT 0x44 17*4882a593Smuzhiyun #define SE401_REQ_SET_BRT 0x45 18*4882a593Smuzhiyun #define SE401_REQ_GET_WIDTH 0x4c 19*4882a593Smuzhiyun #define SE401_REQ_SET_WIDTH 0x4d 20*4882a593Smuzhiyun #define SE401_REQ_GET_HEIGHT 0x4e 21*4882a593Smuzhiyun #define SE401_REQ_SET_HEIGHT 0x4f 22*4882a593Smuzhiyun #define SE401_REQ_GET_OUTPUT_MODE 0x50 23*4882a593Smuzhiyun #define SE401_REQ_SET_OUTPUT_MODE 0x51 24*4882a593Smuzhiyun #define SE401_REQ_GET_EXT_FEATURE 0x52 25*4882a593Smuzhiyun #define SE401_REQ_SET_EXT_FEATURE 0x53 26*4882a593Smuzhiyun #define SE401_REQ_CAMERA_POWER 0x56 27*4882a593Smuzhiyun #define SE401_REQ_LED_CONTROL 0x57 28*4882a593Smuzhiyun #define SE401_REQ_BIOS 0xff 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun #define SE401_BIOS_READ 0x07 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun #define SE401_FORMAT_BAYER 0x40 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun /* Hyundai hv7131b registers 35*4882a593Smuzhiyun 7121 and 7141 should be the same (haven't really checked...) */ 36*4882a593Smuzhiyun /* Mode registers: */ 37*4882a593Smuzhiyun #define HV7131_REG_MODE_A 0x00 38*4882a593Smuzhiyun #define HV7131_REG_MODE_B 0x01 39*4882a593Smuzhiyun #define HV7131_REG_MODE_C 0x02 40*4882a593Smuzhiyun /* Frame registers: */ 41*4882a593Smuzhiyun #define HV7131_REG_FRSU 0x10 42*4882a593Smuzhiyun #define HV7131_REG_FRSL 0x11 43*4882a593Smuzhiyun #define HV7131_REG_FCSU 0x12 44*4882a593Smuzhiyun #define HV7131_REG_FCSL 0x13 45*4882a593Smuzhiyun #define HV7131_REG_FWHU 0x14 46*4882a593Smuzhiyun #define HV7131_REG_FWHL 0x15 47*4882a593Smuzhiyun #define HV7131_REG_FWWU 0x16 48*4882a593Smuzhiyun #define HV7131_REG_FWWL 0x17 49*4882a593Smuzhiyun /* Timing registers: */ 50*4882a593Smuzhiyun #define HV7131_REG_THBU 0x20 51*4882a593Smuzhiyun #define HV7131_REG_THBL 0x21 52*4882a593Smuzhiyun #define HV7131_REG_TVBU 0x22 53*4882a593Smuzhiyun #define HV7131_REG_TVBL 0x23 54*4882a593Smuzhiyun #define HV7131_REG_TITU 0x25 55*4882a593Smuzhiyun #define HV7131_REG_TITM 0x26 56*4882a593Smuzhiyun #define HV7131_REG_TITL 0x27 57*4882a593Smuzhiyun #define HV7131_REG_TMCD 0x28 58*4882a593Smuzhiyun /* Adjust Registers: */ 59*4882a593Smuzhiyun #define HV7131_REG_ARLV 0x30 60*4882a593Smuzhiyun #define HV7131_REG_ARCG 0x31 61*4882a593Smuzhiyun #define HV7131_REG_AGCG 0x32 62*4882a593Smuzhiyun #define HV7131_REG_ABCG 0x33 63*4882a593Smuzhiyun #define HV7131_REG_APBV 0x34 64*4882a593Smuzhiyun #define HV7131_REG_ASLP 0x54 65*4882a593Smuzhiyun /* Offset Registers: */ 66*4882a593Smuzhiyun #define HV7131_REG_OFSR 0x50 67*4882a593Smuzhiyun #define HV7131_REG_OFSG 0x51 68*4882a593Smuzhiyun #define HV7131_REG_OFSB 0x52 69*4882a593Smuzhiyun /* REset level statistics registers: */ 70*4882a593Smuzhiyun #define HV7131_REG_LOREFNOH 0x57 71*4882a593Smuzhiyun #define HV7131_REG_LOREFNOL 0x58 72*4882a593Smuzhiyun #define HV7131_REG_HIREFNOH 0x59 73*4882a593Smuzhiyun #define HV7131_REG_HIREFNOL 0x5a 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun /* se401 registers */ 76*4882a593Smuzhiyun #define SE401_OPERATINGMODE 0x2000 77