Searched +full:qoriq +full:- +full:tmu (Results 1 – 15 of 15) sorted by relevance
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)3 ---4 $id: http://devicetree.org/schemas/thermal/qoriq-thermal.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#7 title: Thermal Monitoring Unit (TMU) on Freescale QorIQ SoCs10 - Anson Huang <Anson.Huang@nxp.com>15 The version of the device is determined by the TMU IP Block Revision19 ---------- -----22 - fsl,qoriq-tmu23 - fsl,imx8mq-tmu[all …]
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)3 * Device Tree Include file for Freescale Layerscape-2080A family SoC.12 #include <dt-bindings/thermal/thermal.h>13 #include <dt-bindings/interrupt-controller/arm-gic.h>17 interrupt-parent = <&gic>;18 #address-cells = <2>;19 #size-cells = <2>;31 #address-cells = <1>;32 #size-cells = <0>;38 /* DRAM space - 1, size : 2 GB DRAM */[all …]
1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)3 // Device Tree Include file for Layerscape-LX2160A family SoC.5 // Copyright 2018-2020 NXP7 #include <dt-bindings/gpio/gpio.h>8 #include <dt-bindings/interrupt-controller/arm-gic.h>9 #include <dt-bindings/thermal/thermal.h>15 interrupt-parent = <&gic>;16 #address-cells = <2>;17 #size-cells = <2>;24 #address-cells = <1>;[all …]
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)3 * Device Tree Include file for NXP Layerscape-1088A family SoC.5 * Copyright 2017-2020 NXP10 #include <dt-bindings/interrupt-controller/arm-gic.h>11 #include <dt-bindings/thermal/thermal.h>15 interrupt-parent = <&gic>;16 #address-cells = <2>;17 #size-cells = <2>;25 #address-cells = <1>;26 #size-cells = <0>;[all …]
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)3 * Device Tree Include file for NXP Layerscape-1046A family SoC.11 #include <dt-bindings/interrupt-controller/arm-gic.h>12 #include <dt-bindings/thermal/thermal.h>16 interrupt-parent = <&gic>;17 #address-cells = <2>;18 #size-cells = <2>;35 #address-cells = <1>;36 #size-cells = <0>;40 compatible = "arm,cortex-a72";[all …]
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)3 * Device Tree Include file for NXP Layerscape-1043A family SoC.5 * Copyright 2014-2015 Freescale Semiconductor, Inc.11 #include <dt-bindings/thermal/thermal.h>12 #include <dt-bindings/interrupt-controller/arm-gic.h>16 interrupt-parent = <&gic>;17 #address-cells = <2>;18 #size-cells = <2>;34 #address-cells = <1>;35 #size-cells = <0>;[all …]
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)3 * Device Tree Include file for NXP Layerscape-1012A family SoC.6 * Copyright 2019-2020 NXP10 #include <dt-bindings/interrupt-controller/arm-gic.h>11 #include <dt-bindings/thermal/thermal.h>15 interrupt-parent = <&gic>;16 #address-cells = <2>;17 #size-cells = <2>;22 rtic-a = &rtic_a;23 rtic-b = &rtic_b;[all …]
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)3 * Device Tree Include file for NXP Layerscape-1028A family SoC.5 * Copyright 2018-2020 NXP11 #include <dt-bindings/interrupt-controller/arm-gic.h>12 #include <dt-bindings/thermal/thermal.h>16 interrupt-parent = <&gic>;17 #address-cells = <2>;18 #size-cells = <2>;25 #address-cells = <1>;26 #size-cells = <0>;[all …]
35 #include <dt-bindings/thermal/thermal.h>38 compatible = "fsl,bman-fbpr";39 alloc-ranges = <0 0 0x10000 0>;43 compatible = "fsl,qman-fqd";44 alloc-ranges = <0 0 0x10000 0>;48 compatible = "fsl,qman-pfdr";49 alloc-ranges = <0 0 0x10000 0>;53 #address-cells = <2>;54 #size-cells = <1>;55 compatible = "fsl,ifc", "simple-bus";[all …]
4 * Copyright 2013 - 2014 Freescale Semiconductor Inc.35 #include <dt-bindings/thermal/thermal.h>38 compatible = "fsl,bman-fbpr";39 alloc-ranges = <0 0 0x10000 0>;43 compatible = "fsl,qman-fqd";44 alloc-ranges = <0 0 0x10000 0>;48 compatible = "fsl,qman-pfdr";49 alloc-ranges = <0 0 0x10000 0>;53 #address-cells = <2>;54 #size-cells = <1>;[all …]
1 // SPDX-License-Identifier: GPL-2.055 #define REGS_V2_TMSAR(n) (0x304 + 16 * (n)) /* TMU monitoring82 return container_of(s, struct qoriq_tmu_data, sensor[s->id]); in qoriq_sensor_to_data()93 * For TMU Rev1: in tmu_get_temp()101 * For TMU Rev2: in tmu_get_temp()109 if (regmap_read_poll_timeout(qdata->regmap, in tmu_get_temp()110 REGS_TRITSR(qsensor->id), in tmu_get_temp()115 return -ENODATA; in tmu_get_temp()117 if (qdata->ver == TMU_VER1) in tmu_get_temp()134 if (qdata->ver == TMU_VER1) { in qoriq_tmu_register_tmu_zone()[all …]
1 # SPDX-License-Identifier: GPL-2.0-only37 int "Emergency poweroff delay in milli-seconds"130 bool "Fair-share thermal governor"132 Enable this to manage platform thermals using fair-share governor.226 memory-mapped reads to get the temperature. Any HW/System that227 allows temperature reading by a single memory-mapped reading, be it270 Support for Thermal Monitoring Unit (TMU) found on Freescale i.MX8MM SoC.281 - AM654296 tristate "QorIQ Thermal Monitoring Unit"301 Support for Thermal Monitoring Unit (TMU) found on QorIQ platforms.[all …]
2 * Copyright 2013-2014 Freescale Semiconductor, Inc.4 * This file is dual-licensed: you can use it either under the terms22 * MA 02110-1301 USA48 #include <dt-bindings/interrupt-controller/arm-gic.h>49 #include <dt-bindings/thermal/thermal.h>52 #address-cells = <2>;53 #size-cells = <2>;55 interrupt-parent = <&gic>;73 #address-cells = <1>;74 #size-cells = <0>;[all …]
11 ---------12 The LS1043A integrated multicore processor combines four ARM Cortex-A5318 - Four 64-bit ARM Cortex-A53 CPUs19 - 1 MB unified L2 Cache20 - One 32-bit DDR3L/DDR4 SDRAM memory controllers with ECC and interleaving22 - Data Path Acceleration Architecture (DPAA) incorporating acceleration the24 - Packet parsing, classification, and distribution (FMan)25 - Queue management for scheduling, packet sequencing, and congestion27 - Hardware buffer management for buffer allocation and de-allocation (BMan)28 - Cryptography acceleration (SEC)[all …]
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