1*4882a593Smuzhiyun/* 2*4882a593Smuzhiyun * T1040 Silicon/SoC Device Tree Source (post include) 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Copyright 2013 - 2014 Freescale Semiconductor Inc. 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * Redistribution and use in source and binary forms, with or without 7*4882a593Smuzhiyun * modification, are permitted provided that the following conditions are met: 8*4882a593Smuzhiyun * * Redistributions of source code must retain the above copyright 9*4882a593Smuzhiyun * notice, this list of conditions and the following disclaimer. 10*4882a593Smuzhiyun * * Redistributions in binary form must reproduce the above copyright 11*4882a593Smuzhiyun * notice, this list of conditions and the following disclaimer in the 12*4882a593Smuzhiyun * documentation and/or other materials provided with the distribution. 13*4882a593Smuzhiyun * * Neither the name of Freescale Semiconductor nor the 14*4882a593Smuzhiyun * names of its contributors may be used to endorse or promote products 15*4882a593Smuzhiyun * derived from this software without specific prior written permission. 16*4882a593Smuzhiyun * 17*4882a593Smuzhiyun * 18*4882a593Smuzhiyun * ALTERNATIVELY, this software may be distributed under the terms of the 19*4882a593Smuzhiyun * GNU General Public License ("GPL") as published by the Free Software 20*4882a593Smuzhiyun * Foundation, either version 2 of that License or (at your option) any 21*4882a593Smuzhiyun * later version. 22*4882a593Smuzhiyun * 23*4882a593Smuzhiyun * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY 24*4882a593Smuzhiyun * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 25*4882a593Smuzhiyun * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 26*4882a593Smuzhiyun * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY 27*4882a593Smuzhiyun * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 28*4882a593Smuzhiyun * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 29*4882a593Smuzhiyun * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 30*4882a593Smuzhiyun * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31*4882a593Smuzhiyun * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 32*4882a593Smuzhiyun * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33*4882a593Smuzhiyun */ 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun#include <dt-bindings/thermal/thermal.h> 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun&bman_fbpr { 38*4882a593Smuzhiyun compatible = "fsl,bman-fbpr"; 39*4882a593Smuzhiyun alloc-ranges = <0 0 0x10000 0>; 40*4882a593Smuzhiyun}; 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun&qman_fqd { 43*4882a593Smuzhiyun compatible = "fsl,qman-fqd"; 44*4882a593Smuzhiyun alloc-ranges = <0 0 0x10000 0>; 45*4882a593Smuzhiyun}; 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun&qman_pfdr { 48*4882a593Smuzhiyun compatible = "fsl,qman-pfdr"; 49*4882a593Smuzhiyun alloc-ranges = <0 0 0x10000 0>; 50*4882a593Smuzhiyun}; 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun&ifc { 53*4882a593Smuzhiyun #address-cells = <2>; 54*4882a593Smuzhiyun #size-cells = <1>; 55*4882a593Smuzhiyun compatible = "fsl,ifc", "simple-bus"; 56*4882a593Smuzhiyun interrupts = <25 2 0 0>; 57*4882a593Smuzhiyun}; 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun&pci0 { 60*4882a593Smuzhiyun compatible = "fsl,t1040-pcie", "fsl,qoriq-pcie-v2.4", "fsl,qoriq-pcie"; 61*4882a593Smuzhiyun device_type = "pci"; 62*4882a593Smuzhiyun #size-cells = <2>; 63*4882a593Smuzhiyun #address-cells = <3>; 64*4882a593Smuzhiyun bus-range = <0x0 0xff>; 65*4882a593Smuzhiyun interrupts = <20 2 0 0>; 66*4882a593Smuzhiyun fsl,iommu-parent = <&pamu0>; 67*4882a593Smuzhiyun pcie@0 { 68*4882a593Smuzhiyun reg = <0 0 0 0 0>; 69*4882a593Smuzhiyun #interrupt-cells = <1>; 70*4882a593Smuzhiyun #size-cells = <2>; 71*4882a593Smuzhiyun #address-cells = <3>; 72*4882a593Smuzhiyun device_type = "pci"; 73*4882a593Smuzhiyun interrupts = <20 2 0 0>; 74*4882a593Smuzhiyun interrupt-map-mask = <0xf800 0 0 7>; 75*4882a593Smuzhiyun interrupt-map = < 76*4882a593Smuzhiyun /* IDSEL 0x0 */ 77*4882a593Smuzhiyun 0000 0 0 1 &mpic 40 1 0 0 78*4882a593Smuzhiyun 0000 0 0 2 &mpic 1 1 0 0 79*4882a593Smuzhiyun 0000 0 0 3 &mpic 2 1 0 0 80*4882a593Smuzhiyun 0000 0 0 4 &mpic 3 1 0 0 81*4882a593Smuzhiyun >; 82*4882a593Smuzhiyun }; 83*4882a593Smuzhiyun}; 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun&pci1 { 86*4882a593Smuzhiyun compatible = "fsl,t1040-pcie", "fsl,qoriq-pcie-v2.4", "fsl,qoriq-pcie"; 87*4882a593Smuzhiyun device_type = "pci"; 88*4882a593Smuzhiyun #size-cells = <2>; 89*4882a593Smuzhiyun #address-cells = <3>; 90*4882a593Smuzhiyun bus-range = <0 0xff>; 91*4882a593Smuzhiyun interrupts = <21 2 0 0>; 92*4882a593Smuzhiyun fsl,iommu-parent = <&pamu0>; 93*4882a593Smuzhiyun pcie@0 { 94*4882a593Smuzhiyun reg = <0 0 0 0 0>; 95*4882a593Smuzhiyun #interrupt-cells = <1>; 96*4882a593Smuzhiyun #size-cells = <2>; 97*4882a593Smuzhiyun #address-cells = <3>; 98*4882a593Smuzhiyun device_type = "pci"; 99*4882a593Smuzhiyun interrupts = <21 2 0 0>; 100*4882a593Smuzhiyun interrupt-map-mask = <0xf800 0 0 7>; 101*4882a593Smuzhiyun interrupt-map = < 102*4882a593Smuzhiyun /* IDSEL 0x0 */ 103*4882a593Smuzhiyun 0000 0 0 1 &mpic 41 1 0 0 104*4882a593Smuzhiyun 0000 0 0 2 &mpic 5 1 0 0 105*4882a593Smuzhiyun 0000 0 0 3 &mpic 6 1 0 0 106*4882a593Smuzhiyun 0000 0 0 4 &mpic 7 1 0 0 107*4882a593Smuzhiyun >; 108*4882a593Smuzhiyun }; 109*4882a593Smuzhiyun}; 110*4882a593Smuzhiyun 111*4882a593Smuzhiyun&pci2 { 112*4882a593Smuzhiyun compatible = "fsl,t1040-pcie", "fsl,qoriq-pcie-v2.4", "fsl,qoriq-pcie"; 113*4882a593Smuzhiyun device_type = "pci"; 114*4882a593Smuzhiyun #size-cells = <2>; 115*4882a593Smuzhiyun #address-cells = <3>; 116*4882a593Smuzhiyun bus-range = <0x0 0xff>; 117*4882a593Smuzhiyun interrupts = <22 2 0 0>; 118*4882a593Smuzhiyun fsl,iommu-parent = <&pamu0>; 119*4882a593Smuzhiyun pcie@0 { 120*4882a593Smuzhiyun reg = <0 0 0 0 0>; 121*4882a593Smuzhiyun #interrupt-cells = <1>; 122*4882a593Smuzhiyun #size-cells = <2>; 123*4882a593Smuzhiyun #address-cells = <3>; 124*4882a593Smuzhiyun device_type = "pci"; 125*4882a593Smuzhiyun interrupts = <22 2 0 0>; 126*4882a593Smuzhiyun interrupt-map-mask = <0xf800 0 0 7>; 127*4882a593Smuzhiyun interrupt-map = < 128*4882a593Smuzhiyun /* IDSEL 0x0 */ 129*4882a593Smuzhiyun 0000 0 0 1 &mpic 42 1 0 0 130*4882a593Smuzhiyun 0000 0 0 2 &mpic 9 1 0 0 131*4882a593Smuzhiyun 0000 0 0 3 &mpic 10 1 0 0 132*4882a593Smuzhiyun 0000 0 0 4 &mpic 11 1 0 0 133*4882a593Smuzhiyun >; 134*4882a593Smuzhiyun }; 135*4882a593Smuzhiyun}; 136*4882a593Smuzhiyun 137*4882a593Smuzhiyun&pci3 { 138*4882a593Smuzhiyun compatible = "fsl,t1040-pcie", "fsl,qoriq-pcie-v2.4", "fsl,qoriq-pcie"; 139*4882a593Smuzhiyun device_type = "pci"; 140*4882a593Smuzhiyun #size-cells = <2>; 141*4882a593Smuzhiyun #address-cells = <3>; 142*4882a593Smuzhiyun bus-range = <0x0 0xff>; 143*4882a593Smuzhiyun interrupts = <23 2 0 0>; 144*4882a593Smuzhiyun fsl,iommu-parent = <&pamu0>; 145*4882a593Smuzhiyun pcie@0 { 146*4882a593Smuzhiyun reg = <0 0 0 0 0>; 147*4882a593Smuzhiyun #interrupt-cells = <1>; 148*4882a593Smuzhiyun #size-cells = <2>; 149*4882a593Smuzhiyun #address-cells = <3>; 150*4882a593Smuzhiyun device_type = "pci"; 151*4882a593Smuzhiyun interrupts = <23 2 0 0>; 152*4882a593Smuzhiyun interrupt-map-mask = <0xf800 0 0 7>; 153*4882a593Smuzhiyun interrupt-map = < 154*4882a593Smuzhiyun /* IDSEL 0x0 */ 155*4882a593Smuzhiyun 0000 0 0 1 &mpic 43 1 0 0 156*4882a593Smuzhiyun 0000 0 0 2 &mpic 0 1 0 0 157*4882a593Smuzhiyun 0000 0 0 3 &mpic 4 1 0 0 158*4882a593Smuzhiyun 0000 0 0 4 &mpic 8 1 0 0 159*4882a593Smuzhiyun >; 160*4882a593Smuzhiyun }; 161*4882a593Smuzhiyun}; 162*4882a593Smuzhiyun 163*4882a593Smuzhiyun&dcsr { 164*4882a593Smuzhiyun #address-cells = <1>; 165*4882a593Smuzhiyun #size-cells = <1>; 166*4882a593Smuzhiyun compatible = "fsl,dcsr", "simple-bus"; 167*4882a593Smuzhiyun 168*4882a593Smuzhiyun dcsr-epu@0 { 169*4882a593Smuzhiyun compatible = "fsl,t1040-dcsr-epu", "fsl,dcsr-epu"; 170*4882a593Smuzhiyun interrupts = <52 2 0 0 171*4882a593Smuzhiyun 84 2 0 0 172*4882a593Smuzhiyun 85 2 0 0>; 173*4882a593Smuzhiyun reg = <0x0 0x1000>; 174*4882a593Smuzhiyun }; 175*4882a593Smuzhiyun dcsr-npc { 176*4882a593Smuzhiyun compatible = "fsl,t1040-dcsr-cnpc", "fsl,dcsr-cnpc"; 177*4882a593Smuzhiyun reg = <0x1000 0x1000 0x1002000 0x10000>; 178*4882a593Smuzhiyun }; 179*4882a593Smuzhiyun dcsr-nxc@2000 { 180*4882a593Smuzhiyun compatible = "fsl,dcsr-nxc"; 181*4882a593Smuzhiyun reg = <0x2000 0x1000>; 182*4882a593Smuzhiyun }; 183*4882a593Smuzhiyun dcsr-corenet { 184*4882a593Smuzhiyun compatible = "fsl,dcsr-corenet"; 185*4882a593Smuzhiyun reg = <0x8000 0x1000 0x1A000 0x1000>; 186*4882a593Smuzhiyun }; 187*4882a593Smuzhiyun dcsr-dpaa@9000 { 188*4882a593Smuzhiyun compatible = "fsl,t1040-dcsr-dpaa", "fsl,dcsr-dpaa"; 189*4882a593Smuzhiyun reg = <0x9000 0x1000>; 190*4882a593Smuzhiyun }; 191*4882a593Smuzhiyun dcsr-ocn@11000 { 192*4882a593Smuzhiyun compatible = "fsl,t1040-dcsr-ocn", "fsl,dcsr-ocn"; 193*4882a593Smuzhiyun reg = <0x11000 0x1000>; 194*4882a593Smuzhiyun }; 195*4882a593Smuzhiyun dcsr-ddr@12000 { 196*4882a593Smuzhiyun compatible = "fsl,dcsr-ddr"; 197*4882a593Smuzhiyun dev-handle = <&ddr1>; 198*4882a593Smuzhiyun reg = <0x12000 0x1000>; 199*4882a593Smuzhiyun }; 200*4882a593Smuzhiyun dcsr-nal@18000 { 201*4882a593Smuzhiyun compatible = "fsl,t1040-dcsr-nal", "fsl,dcsr-nal"; 202*4882a593Smuzhiyun reg = <0x18000 0x1000>; 203*4882a593Smuzhiyun }; 204*4882a593Smuzhiyun dcsr-rcpm@22000 { 205*4882a593Smuzhiyun compatible = "fsl,t1040-dcsr-rcpm", "fsl,dcsr-rcpm"; 206*4882a593Smuzhiyun reg = <0x22000 0x1000>; 207*4882a593Smuzhiyun }; 208*4882a593Smuzhiyun dcsr-snpc@30000 { 209*4882a593Smuzhiyun compatible = "fsl,t1040-dcsr-snpc", "fsl,dcsr-snpc"; 210*4882a593Smuzhiyun reg = <0x30000 0x1000 0x1022000 0x10000>; 211*4882a593Smuzhiyun }; 212*4882a593Smuzhiyun dcsr-snpc@31000 { 213*4882a593Smuzhiyun compatible = "fsl,t1040-dcsr-snpc", "fsl,dcsr-snpc"; 214*4882a593Smuzhiyun reg = <0x31000 0x1000 0x1042000 0x10000>; 215*4882a593Smuzhiyun }; 216*4882a593Smuzhiyun dcsr-cpu-sb-proxy@100000 { 217*4882a593Smuzhiyun compatible = "fsl,dcsr-e5500-sb-proxy", "fsl,dcsr-cpu-sb-proxy"; 218*4882a593Smuzhiyun cpu-handle = <&cpu0>; 219*4882a593Smuzhiyun reg = <0x100000 0x1000 0x101000 0x1000>; 220*4882a593Smuzhiyun }; 221*4882a593Smuzhiyun dcsr-cpu-sb-proxy@108000 { 222*4882a593Smuzhiyun compatible = "fsl,dcsr-e5500-sb-proxy", "fsl,dcsr-cpu-sb-proxy"; 223*4882a593Smuzhiyun cpu-handle = <&cpu1>; 224*4882a593Smuzhiyun reg = <0x108000 0x1000 0x109000 0x1000>; 225*4882a593Smuzhiyun }; 226*4882a593Smuzhiyun dcsr-cpu-sb-proxy@110000 { 227*4882a593Smuzhiyun compatible = "fsl,dcsr-e5500-sb-proxy", "fsl,dcsr-cpu-sb-proxy"; 228*4882a593Smuzhiyun cpu-handle = <&cpu2>; 229*4882a593Smuzhiyun reg = <0x110000 0x1000 0x111000 0x1000>; 230*4882a593Smuzhiyun }; 231*4882a593Smuzhiyun dcsr-cpu-sb-proxy@118000 { 232*4882a593Smuzhiyun compatible = "fsl,dcsr-e5500-sb-proxy", "fsl,dcsr-cpu-sb-proxy"; 233*4882a593Smuzhiyun cpu-handle = <&cpu3>; 234*4882a593Smuzhiyun reg = <0x118000 0x1000 0x119000 0x1000>; 235*4882a593Smuzhiyun }; 236*4882a593Smuzhiyun}; 237*4882a593Smuzhiyun 238*4882a593Smuzhiyun&bportals { 239*4882a593Smuzhiyun #address-cells = <0x1>; 240*4882a593Smuzhiyun #size-cells = <0x1>; 241*4882a593Smuzhiyun compatible = "simple-bus"; 242*4882a593Smuzhiyun 243*4882a593Smuzhiyun bman-portal@0 { 244*4882a593Smuzhiyun compatible = "fsl,bman-portal"; 245*4882a593Smuzhiyun reg = <0x0 0x4000>, <0x1000000 0x1000>; 246*4882a593Smuzhiyun interrupts = <105 2 0 0>; 247*4882a593Smuzhiyun }; 248*4882a593Smuzhiyun bman-portal@4000 { 249*4882a593Smuzhiyun compatible = "fsl,bman-portal"; 250*4882a593Smuzhiyun reg = <0x4000 0x4000>, <0x1001000 0x1000>; 251*4882a593Smuzhiyun interrupts = <107 2 0 0>; 252*4882a593Smuzhiyun }; 253*4882a593Smuzhiyun bman-portal@8000 { 254*4882a593Smuzhiyun compatible = "fsl,bman-portal"; 255*4882a593Smuzhiyun reg = <0x8000 0x4000>, <0x1002000 0x1000>; 256*4882a593Smuzhiyun interrupts = <109 2 0 0>; 257*4882a593Smuzhiyun }; 258*4882a593Smuzhiyun bman-portal@c000 { 259*4882a593Smuzhiyun compatible = "fsl,bman-portal"; 260*4882a593Smuzhiyun reg = <0xc000 0x4000>, <0x1003000 0x1000>; 261*4882a593Smuzhiyun interrupts = <111 2 0 0>; 262*4882a593Smuzhiyun }; 263*4882a593Smuzhiyun bman-portal@10000 { 264*4882a593Smuzhiyun compatible = "fsl,bman-portal"; 265*4882a593Smuzhiyun reg = <0x10000 0x4000>, <0x1004000 0x1000>; 266*4882a593Smuzhiyun interrupts = <113 2 0 0>; 267*4882a593Smuzhiyun }; 268*4882a593Smuzhiyun bman-portal@14000 { 269*4882a593Smuzhiyun compatible = "fsl,bman-portal"; 270*4882a593Smuzhiyun reg = <0x14000 0x4000>, <0x1005000 0x1000>; 271*4882a593Smuzhiyun interrupts = <115 2 0 0>; 272*4882a593Smuzhiyun }; 273*4882a593Smuzhiyun bman-portal@18000 { 274*4882a593Smuzhiyun compatible = "fsl,bman-portal"; 275*4882a593Smuzhiyun reg = <0x18000 0x4000>, <0x1006000 0x1000>; 276*4882a593Smuzhiyun interrupts = <117 2 0 0>; 277*4882a593Smuzhiyun }; 278*4882a593Smuzhiyun bman-portal@1c000 { 279*4882a593Smuzhiyun compatible = "fsl,bman-portal"; 280*4882a593Smuzhiyun reg = <0x1c000 0x4000>, <0x1007000 0x1000>; 281*4882a593Smuzhiyun interrupts = <119 2 0 0>; 282*4882a593Smuzhiyun }; 283*4882a593Smuzhiyun bman-portal@20000 { 284*4882a593Smuzhiyun compatible = "fsl,bman-portal"; 285*4882a593Smuzhiyun reg = <0x20000 0x4000>, <0x1008000 0x1000>; 286*4882a593Smuzhiyun interrupts = <121 2 0 0>; 287*4882a593Smuzhiyun }; 288*4882a593Smuzhiyun bman-portal@24000 { 289*4882a593Smuzhiyun compatible = "fsl,bman-portal"; 290*4882a593Smuzhiyun reg = <0x24000 0x4000>, <0x1009000 0x1000>; 291*4882a593Smuzhiyun interrupts = <123 2 0 0>; 292*4882a593Smuzhiyun }; 293*4882a593Smuzhiyun}; 294*4882a593Smuzhiyun 295*4882a593Smuzhiyun&qportals { 296*4882a593Smuzhiyun #address-cells = <0x1>; 297*4882a593Smuzhiyun #size-cells = <0x1>; 298*4882a593Smuzhiyun compatible = "simple-bus"; 299*4882a593Smuzhiyun 300*4882a593Smuzhiyun qportal0: qman-portal@0 { 301*4882a593Smuzhiyun compatible = "fsl,qman-portal"; 302*4882a593Smuzhiyun reg = <0x0 0x4000>, <0x1000000 0x1000>; 303*4882a593Smuzhiyun interrupts = <104 0x2 0 0>; 304*4882a593Smuzhiyun cell-index = <0x0>; 305*4882a593Smuzhiyun }; 306*4882a593Smuzhiyun qportal1: qman-portal@4000 { 307*4882a593Smuzhiyun compatible = "fsl,qman-portal"; 308*4882a593Smuzhiyun reg = <0x4000 0x4000>, <0x1001000 0x1000>; 309*4882a593Smuzhiyun interrupts = <106 0x2 0 0>; 310*4882a593Smuzhiyun cell-index = <0x1>; 311*4882a593Smuzhiyun }; 312*4882a593Smuzhiyun qportal2: qman-portal@8000 { 313*4882a593Smuzhiyun compatible = "fsl,qman-portal"; 314*4882a593Smuzhiyun reg = <0x8000 0x4000>, <0x1002000 0x1000>; 315*4882a593Smuzhiyun interrupts = <108 0x2 0 0>; 316*4882a593Smuzhiyun cell-index = <0x2>; 317*4882a593Smuzhiyun }; 318*4882a593Smuzhiyun qportal3: qman-portal@c000 { 319*4882a593Smuzhiyun compatible = "fsl,qman-portal"; 320*4882a593Smuzhiyun reg = <0xc000 0x4000>, <0x1003000 0x1000>; 321*4882a593Smuzhiyun interrupts = <110 0x2 0 0>; 322*4882a593Smuzhiyun cell-index = <0x3>; 323*4882a593Smuzhiyun }; 324*4882a593Smuzhiyun qportal4: qman-portal@10000 { 325*4882a593Smuzhiyun compatible = "fsl,qman-portal"; 326*4882a593Smuzhiyun reg = <0x10000 0x4000>, <0x1004000 0x1000>; 327*4882a593Smuzhiyun interrupts = <112 0x2 0 0>; 328*4882a593Smuzhiyun cell-index = <0x4>; 329*4882a593Smuzhiyun }; 330*4882a593Smuzhiyun qportal5: qman-portal@14000 { 331*4882a593Smuzhiyun compatible = "fsl,qman-portal"; 332*4882a593Smuzhiyun reg = <0x14000 0x4000>, <0x1005000 0x1000>; 333*4882a593Smuzhiyun interrupts = <114 0x2 0 0>; 334*4882a593Smuzhiyun cell-index = <0x5>; 335*4882a593Smuzhiyun }; 336*4882a593Smuzhiyun qportal6: qman-portal@18000 { 337*4882a593Smuzhiyun compatible = "fsl,qman-portal"; 338*4882a593Smuzhiyun reg = <0x18000 0x4000>, <0x1006000 0x1000>; 339*4882a593Smuzhiyun interrupts = <116 0x2 0 0>; 340*4882a593Smuzhiyun cell-index = <0x6>; 341*4882a593Smuzhiyun }; 342*4882a593Smuzhiyun qportal7: qman-portal@1c000 { 343*4882a593Smuzhiyun compatible = "fsl,qman-portal"; 344*4882a593Smuzhiyun reg = <0x1c000 0x4000>, <0x1007000 0x1000>; 345*4882a593Smuzhiyun interrupts = <118 0x2 0 0>; 346*4882a593Smuzhiyun cell-index = <0x7>; 347*4882a593Smuzhiyun }; 348*4882a593Smuzhiyun qportal8: qman-portal@20000 { 349*4882a593Smuzhiyun compatible = "fsl,qman-portal"; 350*4882a593Smuzhiyun reg = <0x20000 0x4000>, <0x1008000 0x1000>; 351*4882a593Smuzhiyun interrupts = <120 0x2 0 0>; 352*4882a593Smuzhiyun cell-index = <0x8>; 353*4882a593Smuzhiyun }; 354*4882a593Smuzhiyun qportal9: qman-portal@24000 { 355*4882a593Smuzhiyun compatible = "fsl,qman-portal"; 356*4882a593Smuzhiyun reg = <0x24000 0x4000>, <0x1009000 0x1000>; 357*4882a593Smuzhiyun interrupts = <122 0x2 0 0>; 358*4882a593Smuzhiyun cell-index = <0x9>; 359*4882a593Smuzhiyun }; 360*4882a593Smuzhiyun}; 361*4882a593Smuzhiyun 362*4882a593Smuzhiyun&soc { 363*4882a593Smuzhiyun #address-cells = <1>; 364*4882a593Smuzhiyun #size-cells = <1>; 365*4882a593Smuzhiyun device_type = "soc"; 366*4882a593Smuzhiyun compatible = "simple-bus"; 367*4882a593Smuzhiyun 368*4882a593Smuzhiyun soc-sram-error { 369*4882a593Smuzhiyun compatible = "fsl,soc-sram-error"; 370*4882a593Smuzhiyun interrupts = <16 2 1 29>; 371*4882a593Smuzhiyun }; 372*4882a593Smuzhiyun 373*4882a593Smuzhiyun corenet-law@0 { 374*4882a593Smuzhiyun compatible = "fsl,corenet-law"; 375*4882a593Smuzhiyun reg = <0x0 0x1000>; 376*4882a593Smuzhiyun fsl,num-laws = <16>; 377*4882a593Smuzhiyun }; 378*4882a593Smuzhiyun 379*4882a593Smuzhiyun ddr1: memory-controller@8000 { 380*4882a593Smuzhiyun compatible = "fsl,qoriq-memory-controller-v5.0", 381*4882a593Smuzhiyun "fsl,qoriq-memory-controller"; 382*4882a593Smuzhiyun reg = <0x8000 0x1000>; 383*4882a593Smuzhiyun interrupts = <16 2 1 23>; 384*4882a593Smuzhiyun }; 385*4882a593Smuzhiyun 386*4882a593Smuzhiyun cpc: l3-cache-controller@10000 { 387*4882a593Smuzhiyun compatible = "fsl,t1040-l3-cache-controller", "cache"; 388*4882a593Smuzhiyun reg = <0x10000 0x1000>; 389*4882a593Smuzhiyun interrupts = <16 2 1 27>; 390*4882a593Smuzhiyun }; 391*4882a593Smuzhiyun 392*4882a593Smuzhiyun corenet-cf@18000 { 393*4882a593Smuzhiyun compatible = "fsl,corenet2-cf", "fsl,corenet-cf"; 394*4882a593Smuzhiyun reg = <0x18000 0x1000>; 395*4882a593Smuzhiyun interrupts = <16 2 1 31>; 396*4882a593Smuzhiyun fsl,ccf-num-csdids = <32>; 397*4882a593Smuzhiyun fsl,ccf-num-snoopids = <32>; 398*4882a593Smuzhiyun }; 399*4882a593Smuzhiyun 400*4882a593Smuzhiyun iommu@20000 { 401*4882a593Smuzhiyun compatible = "fsl,pamu-v1.0", "fsl,pamu"; 402*4882a593Smuzhiyun reg = <0x20000 0x1000>; 403*4882a593Smuzhiyun ranges = <0 0x20000 0x1000>; 404*4882a593Smuzhiyun #address-cells = <1>; 405*4882a593Smuzhiyun #size-cells = <1>; 406*4882a593Smuzhiyun interrupts = < 407*4882a593Smuzhiyun 24 2 0 0 408*4882a593Smuzhiyun 16 2 1 30>; 409*4882a593Smuzhiyun pamu0: pamu@0 { 410*4882a593Smuzhiyun reg = <0 0x1000>; 411*4882a593Smuzhiyun fsl,primary-cache-geometry = <128 1>; 412*4882a593Smuzhiyun fsl,secondary-cache-geometry = <16 2>; 413*4882a593Smuzhiyun }; 414*4882a593Smuzhiyun }; 415*4882a593Smuzhiyun 416*4882a593Smuzhiyun/include/ "qoriq-mpic.dtsi" 417*4882a593Smuzhiyun 418*4882a593Smuzhiyun guts: global-utilities@e0000 { 419*4882a593Smuzhiyun compatible = "fsl,t1040-device-config", "fsl,qoriq-device-config-2.0"; 420*4882a593Smuzhiyun reg = <0xe0000 0xe00>; 421*4882a593Smuzhiyun fsl,has-rstcr; 422*4882a593Smuzhiyun fsl,liodn-bits = <12>; 423*4882a593Smuzhiyun }; 424*4882a593Smuzhiyun 425*4882a593Smuzhiyun/include/ "qoriq-clockgen2.dtsi" 426*4882a593Smuzhiyun global-utilities@e1000 { 427*4882a593Smuzhiyun compatible = "fsl,t1040-clockgen", "fsl,qoriq-clockgen-2.0"; 428*4882a593Smuzhiyun }; 429*4882a593Smuzhiyun 430*4882a593Smuzhiyun rcpm: global-utilities@e2000 { 431*4882a593Smuzhiyun compatible = "fsl,t1040-rcpm", "fsl,qoriq-rcpm-2.1"; 432*4882a593Smuzhiyun reg = <0xe2000 0x1000>; 433*4882a593Smuzhiyun }; 434*4882a593Smuzhiyun 435*4882a593Smuzhiyun sfp: sfp@e8000 { 436*4882a593Smuzhiyun compatible = "fsl,t1040-sfp"; 437*4882a593Smuzhiyun reg = <0xe8000 0x1000>; 438*4882a593Smuzhiyun }; 439*4882a593Smuzhiyun 440*4882a593Smuzhiyun serdes: serdes@ea000 { 441*4882a593Smuzhiyun compatible = "fsl,t1040-serdes"; 442*4882a593Smuzhiyun reg = <0xea000 0x4000>; 443*4882a593Smuzhiyun }; 444*4882a593Smuzhiyun 445*4882a593Smuzhiyun tmu: tmu@f0000 { 446*4882a593Smuzhiyun compatible = "fsl,qoriq-tmu"; 447*4882a593Smuzhiyun reg = <0xf0000 0x1000>; 448*4882a593Smuzhiyun interrupts = <18 2 0 0>; 449*4882a593Smuzhiyun fsl,tmu-range = <0xa0000 0x90026 0x8004a 0x1006a>; 450*4882a593Smuzhiyun fsl,tmu-calibration = <0x00000000 0x00000025 451*4882a593Smuzhiyun 0x00000001 0x00000028 452*4882a593Smuzhiyun 0x00000002 0x0000002d 453*4882a593Smuzhiyun 0x00000003 0x00000031 454*4882a593Smuzhiyun 0x00000004 0x00000036 455*4882a593Smuzhiyun 0x00000005 0x0000003a 456*4882a593Smuzhiyun 0x00000006 0x00000040 457*4882a593Smuzhiyun 0x00000007 0x00000044 458*4882a593Smuzhiyun 0x00000008 0x0000004a 459*4882a593Smuzhiyun 0x00000009 0x0000004f 460*4882a593Smuzhiyun 0x0000000a 0x00000054 461*4882a593Smuzhiyun 462*4882a593Smuzhiyun 0x00010000 0x0000000d 463*4882a593Smuzhiyun 0x00010001 0x00000013 464*4882a593Smuzhiyun 0x00010002 0x00000019 465*4882a593Smuzhiyun 0x00010003 0x0000001f 466*4882a593Smuzhiyun 0x00010004 0x00000025 467*4882a593Smuzhiyun 0x00010005 0x0000002d 468*4882a593Smuzhiyun 0x00010006 0x00000033 469*4882a593Smuzhiyun 0x00010007 0x00000043 470*4882a593Smuzhiyun 0x00010008 0x0000004b 471*4882a593Smuzhiyun 0x00010009 0x00000053 472*4882a593Smuzhiyun 473*4882a593Smuzhiyun 0x00020000 0x00000010 474*4882a593Smuzhiyun 0x00020001 0x00000017 475*4882a593Smuzhiyun 0x00020002 0x0000001f 476*4882a593Smuzhiyun 0x00020003 0x00000029 477*4882a593Smuzhiyun 0x00020004 0x00000031 478*4882a593Smuzhiyun 0x00020005 0x0000003c 479*4882a593Smuzhiyun 0x00020006 0x00000042 480*4882a593Smuzhiyun 0x00020007 0x0000004d 481*4882a593Smuzhiyun 0x00020008 0x00000056 482*4882a593Smuzhiyun 483*4882a593Smuzhiyun 0x00030000 0x00000012 484*4882a593Smuzhiyun 0x00030001 0x0000001d>; 485*4882a593Smuzhiyun #thermal-sensor-cells = <1>; 486*4882a593Smuzhiyun }; 487*4882a593Smuzhiyun 488*4882a593Smuzhiyun thermal-zones { 489*4882a593Smuzhiyun cpu_thermal: cpu-thermal { 490*4882a593Smuzhiyun polling-delay-passive = <1000>; 491*4882a593Smuzhiyun polling-delay = <5000>; 492*4882a593Smuzhiyun 493*4882a593Smuzhiyun thermal-sensors = <&tmu 2>; 494*4882a593Smuzhiyun 495*4882a593Smuzhiyun trips { 496*4882a593Smuzhiyun cpu_alert: cpu-alert { 497*4882a593Smuzhiyun temperature = <85000>; 498*4882a593Smuzhiyun hysteresis = <2000>; 499*4882a593Smuzhiyun type = "passive"; 500*4882a593Smuzhiyun }; 501*4882a593Smuzhiyun cpu_crit: cpu-crit { 502*4882a593Smuzhiyun temperature = <95000>; 503*4882a593Smuzhiyun hysteresis = <2000>; 504*4882a593Smuzhiyun type = "critical"; 505*4882a593Smuzhiyun }; 506*4882a593Smuzhiyun }; 507*4882a593Smuzhiyun 508*4882a593Smuzhiyun cooling-maps { 509*4882a593Smuzhiyun map0 { 510*4882a593Smuzhiyun trip = <&cpu_alert>; 511*4882a593Smuzhiyun cooling-device = 512*4882a593Smuzhiyun <&cpu0 THERMAL_NO_LIMIT 513*4882a593Smuzhiyun THERMAL_NO_LIMIT>; 514*4882a593Smuzhiyun }; 515*4882a593Smuzhiyun map1 { 516*4882a593Smuzhiyun trip = <&cpu_alert>; 517*4882a593Smuzhiyun cooling-device = 518*4882a593Smuzhiyun <&cpu1 THERMAL_NO_LIMIT 519*4882a593Smuzhiyun THERMAL_NO_LIMIT>; 520*4882a593Smuzhiyun }; 521*4882a593Smuzhiyun map2 { 522*4882a593Smuzhiyun trip = <&cpu_alert>; 523*4882a593Smuzhiyun cooling-device = 524*4882a593Smuzhiyun <&cpu2 THERMAL_NO_LIMIT 525*4882a593Smuzhiyun THERMAL_NO_LIMIT>; 526*4882a593Smuzhiyun }; 527*4882a593Smuzhiyun map3 { 528*4882a593Smuzhiyun trip = <&cpu_alert>; 529*4882a593Smuzhiyun cooling-device = 530*4882a593Smuzhiyun <&cpu3 THERMAL_NO_LIMIT 531*4882a593Smuzhiyun THERMAL_NO_LIMIT>; 532*4882a593Smuzhiyun }; 533*4882a593Smuzhiyun }; 534*4882a593Smuzhiyun }; 535*4882a593Smuzhiyun }; 536*4882a593Smuzhiyun 537*4882a593Smuzhiyun scfg: global-utilities@fc000 { 538*4882a593Smuzhiyun compatible = "fsl,t1040-scfg"; 539*4882a593Smuzhiyun reg = <0xfc000 0x1000>; 540*4882a593Smuzhiyun }; 541*4882a593Smuzhiyun 542*4882a593Smuzhiyun/include/ "elo3-dma-0.dtsi" 543*4882a593Smuzhiyun/include/ "elo3-dma-1.dtsi" 544*4882a593Smuzhiyun/include/ "qoriq-espi-0.dtsi" 545*4882a593Smuzhiyun spi@110000 { 546*4882a593Smuzhiyun fsl,espi-num-chipselects = <4>; 547*4882a593Smuzhiyun }; 548*4882a593Smuzhiyun 549*4882a593Smuzhiyun/include/ "qoriq-esdhc-0.dtsi" 550*4882a593Smuzhiyun sdhc@114000 { 551*4882a593Smuzhiyun compatible = "fsl,t1040-esdhc", "fsl,esdhc"; 552*4882a593Smuzhiyun fsl,iommu-parent = <&pamu0>; 553*4882a593Smuzhiyun fsl,liodn-reg = <&guts 0x530>; /* eSDHCLIODNR */ 554*4882a593Smuzhiyun sdhci,auto-cmd12; 555*4882a593Smuzhiyun }; 556*4882a593Smuzhiyun/include/ "qoriq-i2c-0.dtsi" 557*4882a593Smuzhiyun/include/ "qoriq-i2c-1.dtsi" 558*4882a593Smuzhiyun/include/ "qoriq-duart-0.dtsi" 559*4882a593Smuzhiyun/include/ "qoriq-duart-1.dtsi" 560*4882a593Smuzhiyun/include/ "qoriq-gpio-0.dtsi" 561*4882a593Smuzhiyun/include/ "qoriq-gpio-1.dtsi" 562*4882a593Smuzhiyun/include/ "qoriq-gpio-2.dtsi" 563*4882a593Smuzhiyun/include/ "qoriq-gpio-3.dtsi" 564*4882a593Smuzhiyun/include/ "qoriq-usb2-mph-0.dtsi" 565*4882a593Smuzhiyun usb0: usb@210000 { 566*4882a593Smuzhiyun compatible = "fsl-usb2-mph-v2.5", "fsl-usb2-mph"; 567*4882a593Smuzhiyun fsl,iommu-parent = <&pamu0>; 568*4882a593Smuzhiyun fsl,liodn-reg = <&guts 0x520>; /* USB1LIODNR */ 569*4882a593Smuzhiyun phy_type = "utmi"; 570*4882a593Smuzhiyun port0; 571*4882a593Smuzhiyun }; 572*4882a593Smuzhiyun/include/ "qoriq-usb2-dr-0.dtsi" 573*4882a593Smuzhiyun usb1: usb@211000 { 574*4882a593Smuzhiyun compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr"; 575*4882a593Smuzhiyun fsl,iommu-parent = <&pamu0>; 576*4882a593Smuzhiyun fsl,liodn-reg = <&guts 0x524>; /* USB2LIODNR */ 577*4882a593Smuzhiyun dr_mode = "host"; 578*4882a593Smuzhiyun phy_type = "utmi"; 579*4882a593Smuzhiyun }; 580*4882a593Smuzhiyun 581*4882a593Smuzhiyun display@180000 { 582*4882a593Smuzhiyun compatible = "fsl,t1040-diu", "fsl,diu"; 583*4882a593Smuzhiyun reg = <0x180000 1000>; 584*4882a593Smuzhiyun interrupts = <74 2 0 0>; 585*4882a593Smuzhiyun }; 586*4882a593Smuzhiyun 587*4882a593Smuzhiyun/include/ "qoriq-sata2-0.dtsi" 588*4882a593Smuzhiyun sata@220000 { 589*4882a593Smuzhiyun fsl,iommu-parent = <&pamu0>; 590*4882a593Smuzhiyun fsl,liodn-reg = <&guts 0x550>; /* SATA1LIODNR */ 591*4882a593Smuzhiyun }; 592*4882a593Smuzhiyun/include/ "qoriq-sata2-1.dtsi" 593*4882a593Smuzhiyun sata@221000 { 594*4882a593Smuzhiyun fsl,iommu-parent = <&pamu0>; 595*4882a593Smuzhiyun fsl,liodn-reg = <&guts 0x554>; /* SATA2LIODNR */ 596*4882a593Smuzhiyun }; 597*4882a593Smuzhiyun/include/ "qoriq-sec5.0-0.dtsi" 598*4882a593Smuzhiyun/include/ "qoriq-qman3.dtsi" 599*4882a593Smuzhiyun/include/ "qoriq-bman1.dtsi" 600*4882a593Smuzhiyun 601*4882a593Smuzhiyun/include/ "qoriq-fman3l-0.dtsi" 602*4882a593Smuzhiyun/include/ "qoriq-fman3-0-1g-0.dtsi" 603*4882a593Smuzhiyun/include/ "qoriq-fman3-0-1g-1.dtsi" 604*4882a593Smuzhiyun/include/ "qoriq-fman3-0-1g-2.dtsi" 605*4882a593Smuzhiyun/include/ "qoriq-fman3-0-1g-3.dtsi" 606*4882a593Smuzhiyun/include/ "qoriq-fman3-0-1g-4.dtsi" 607*4882a593Smuzhiyun fman@400000 { 608*4882a593Smuzhiyun enet0: ethernet@e0000 { 609*4882a593Smuzhiyun }; 610*4882a593Smuzhiyun 611*4882a593Smuzhiyun enet1: ethernet@e2000 { 612*4882a593Smuzhiyun }; 613*4882a593Smuzhiyun 614*4882a593Smuzhiyun enet2: ethernet@e4000 { 615*4882a593Smuzhiyun }; 616*4882a593Smuzhiyun 617*4882a593Smuzhiyun enet3: ethernet@e6000 { 618*4882a593Smuzhiyun }; 619*4882a593Smuzhiyun 620*4882a593Smuzhiyun enet4: ethernet@e8000 { 621*4882a593Smuzhiyun }; 622*4882a593Smuzhiyun 623*4882a593Smuzhiyun mdio@fc000 { 624*4882a593Smuzhiyun interrupts = <100 1 0 0>; 625*4882a593Smuzhiyun }; 626*4882a593Smuzhiyun 627*4882a593Smuzhiyun mdio@fd000 { 628*4882a593Smuzhiyun status = "disabled"; 629*4882a593Smuzhiyun }; 630*4882a593Smuzhiyun }; 631*4882a593Smuzhiyun 632*4882a593Smuzhiyun seville_switch: ethernet-switch@800000 { 633*4882a593Smuzhiyun compatible = "mscc,vsc9953-switch"; 634*4882a593Smuzhiyun reg = <0x800000 0x290000>; 635*4882a593Smuzhiyun interrupts = <26 2 0 0>; 636*4882a593Smuzhiyun interrupt-names = "xtr"; 637*4882a593Smuzhiyun little-endian; 638*4882a593Smuzhiyun #address-cells = <1>; 639*4882a593Smuzhiyun #size-cells = <0>; 640*4882a593Smuzhiyun status = "disabled"; 641*4882a593Smuzhiyun 642*4882a593Smuzhiyun ports { 643*4882a593Smuzhiyun #address-cells = <1>; 644*4882a593Smuzhiyun #size-cells = <0>; 645*4882a593Smuzhiyun 646*4882a593Smuzhiyun seville_port0: port@0 { 647*4882a593Smuzhiyun reg = <0>; 648*4882a593Smuzhiyun status = "disabled"; 649*4882a593Smuzhiyun }; 650*4882a593Smuzhiyun 651*4882a593Smuzhiyun seville_port1: port@1 { 652*4882a593Smuzhiyun reg = <1>; 653*4882a593Smuzhiyun status = "disabled"; 654*4882a593Smuzhiyun }; 655*4882a593Smuzhiyun 656*4882a593Smuzhiyun seville_port2: port@2 { 657*4882a593Smuzhiyun reg = <2>; 658*4882a593Smuzhiyun status = "disabled"; 659*4882a593Smuzhiyun }; 660*4882a593Smuzhiyun 661*4882a593Smuzhiyun seville_port3: port@3 { 662*4882a593Smuzhiyun reg = <3>; 663*4882a593Smuzhiyun status = "disabled"; 664*4882a593Smuzhiyun }; 665*4882a593Smuzhiyun 666*4882a593Smuzhiyun seville_port4: port@4 { 667*4882a593Smuzhiyun reg = <4>; 668*4882a593Smuzhiyun status = "disabled"; 669*4882a593Smuzhiyun }; 670*4882a593Smuzhiyun 671*4882a593Smuzhiyun seville_port5: port@5 { 672*4882a593Smuzhiyun reg = <5>; 673*4882a593Smuzhiyun status = "disabled"; 674*4882a593Smuzhiyun }; 675*4882a593Smuzhiyun 676*4882a593Smuzhiyun seville_port6: port@6 { 677*4882a593Smuzhiyun reg = <6>; 678*4882a593Smuzhiyun status = "disabled"; 679*4882a593Smuzhiyun }; 680*4882a593Smuzhiyun 681*4882a593Smuzhiyun seville_port7: port@7 { 682*4882a593Smuzhiyun reg = <7>; 683*4882a593Smuzhiyun status = "disabled"; 684*4882a593Smuzhiyun }; 685*4882a593Smuzhiyun 686*4882a593Smuzhiyun seville_port8: port@8 { 687*4882a593Smuzhiyun reg = <8>; 688*4882a593Smuzhiyun phy-mode = "internal"; 689*4882a593Smuzhiyun status = "disabled"; 690*4882a593Smuzhiyun 691*4882a593Smuzhiyun fixed-link { 692*4882a593Smuzhiyun speed = <2500>; 693*4882a593Smuzhiyun full-duplex; 694*4882a593Smuzhiyun }; 695*4882a593Smuzhiyun }; 696*4882a593Smuzhiyun 697*4882a593Smuzhiyun seville_port9: port@9 { 698*4882a593Smuzhiyun reg = <9>; 699*4882a593Smuzhiyun phy-mode = "internal"; 700*4882a593Smuzhiyun status = "disabled"; 701*4882a593Smuzhiyun 702*4882a593Smuzhiyun fixed-link { 703*4882a593Smuzhiyun speed = <2500>; 704*4882a593Smuzhiyun full-duplex; 705*4882a593Smuzhiyun }; 706*4882a593Smuzhiyun }; 707*4882a593Smuzhiyun }; 708*4882a593Smuzhiyun }; 709*4882a593Smuzhiyun}; 710*4882a593Smuzhiyun 711*4882a593Smuzhiyun&qe { 712*4882a593Smuzhiyun #address-cells = <1>; 713*4882a593Smuzhiyun #size-cells = <1>; 714*4882a593Smuzhiyun device_type = "qe"; 715*4882a593Smuzhiyun compatible = "fsl,qe"; 716*4882a593Smuzhiyun fsl,qe-num-riscs = <1>; 717*4882a593Smuzhiyun fsl,qe-num-snums = <28>; 718*4882a593Smuzhiyun 719*4882a593Smuzhiyun qeic: interrupt-controller@80 { 720*4882a593Smuzhiyun interrupt-controller; 721*4882a593Smuzhiyun compatible = "fsl,qe-ic"; 722*4882a593Smuzhiyun #address-cells = <0>; 723*4882a593Smuzhiyun #interrupt-cells = <1>; 724*4882a593Smuzhiyun reg = <0x80 0x80>; 725*4882a593Smuzhiyun interrupts = <95 2 0 0 94 2 0 0>; //high:79 low:78 726*4882a593Smuzhiyun }; 727*4882a593Smuzhiyun 728*4882a593Smuzhiyun ucc@2000 { 729*4882a593Smuzhiyun cell-index = <1>; 730*4882a593Smuzhiyun reg = <0x2000 0x200>; 731*4882a593Smuzhiyun interrupts = <32>; 732*4882a593Smuzhiyun interrupt-parent = <&qeic>; 733*4882a593Smuzhiyun }; 734*4882a593Smuzhiyun 735*4882a593Smuzhiyun ucc@2200 { 736*4882a593Smuzhiyun cell-index = <3>; 737*4882a593Smuzhiyun reg = <0x2200 0x200>; 738*4882a593Smuzhiyun interrupts = <34>; 739*4882a593Smuzhiyun interrupt-parent = <&qeic>; 740*4882a593Smuzhiyun }; 741*4882a593Smuzhiyun 742*4882a593Smuzhiyun muram@10000 { 743*4882a593Smuzhiyun #address-cells = <1>; 744*4882a593Smuzhiyun #size-cells = <1>; 745*4882a593Smuzhiyun compatible = "fsl,qe-muram", "fsl,cpm-muram"; 746*4882a593Smuzhiyun ranges = <0x0 0x10000 0x6000>; 747*4882a593Smuzhiyun 748*4882a593Smuzhiyun data-only@0 { 749*4882a593Smuzhiyun compatible = "fsl,qe-muram-data", 750*4882a593Smuzhiyun "fsl,cpm-muram-data"; 751*4882a593Smuzhiyun reg = <0x0 0x6000>; 752*4882a593Smuzhiyun }; 753*4882a593Smuzhiyun }; 754*4882a593Smuzhiyun}; 755