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/OK3568_Linux_fs/kernel/drivers/gpu/drm/hisilicon/kirin/kirin/
H A Ddw_drm_dsi.c1 // SPDX-License-Identifier: GPL-2.0-only
6 * Copyright (c) 2014-2016 Hisilicon Limited.
35 static u32 dsi_calc_phy_rate(u32 req_kHz, struct mipi_phy_params *phy) in dsi_calc_phy_rate() argument
65 phy->pll_vco_750M = dphy_range_info[i].pll_vco_750M; in dsi_calc_phy_rate()
66 phy->hstx_ckg_sel = dphy_range_info[i].hstx_ckg_sel; in dsi_calc_phy_rate()
68 if (phy->hstx_ckg_sel <= 7 && in dsi_calc_phy_rate()
69 phy->hstx_ckg_sel >= 4) in dsi_calc_phy_rate()
70 q_pll = 0x10 >> (7 - phy->hstx_ckg_sel); in dsi_calc_phy_rate()
104 phy->pll_fbd_p = 0; in dsi_calc_phy_rate()
105 phy->pll_pre_div1p = 1; in dsi_calc_phy_rate()
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/OK3568_Linux_fs/kernel/drivers/nfc/s3fwrn5/
H A Di2c.c1 // SPDX-License-Identifier: GPL-2.0-or-later
34 enum s3fwrn5_mode mode; member
40 struct s3fwrn5_i2c_phy *phy = phy_id; in s3fwrn5_i2c_set_wake() local
42 mutex_lock(&phy->mutex); in s3fwrn5_i2c_set_wake()
43 gpio_set_value(phy->gpio_fw_wake, wake); in s3fwrn5_i2c_set_wake()
45 mutex_unlock(&phy->mutex); in s3fwrn5_i2c_set_wake()
48 static void s3fwrn5_i2c_set_mode(void *phy_id, enum s3fwrn5_mode mode) in s3fwrn5_i2c_set_mode() argument
50 struct s3fwrn5_i2c_phy *phy = phy_id; in s3fwrn5_i2c_set_mode() local
52 mutex_lock(&phy->mutex); in s3fwrn5_i2c_set_mode()
54 if (phy->mode == mode) in s3fwrn5_i2c_set_mode()
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/OK3568_Linux_fs/u-boot/include/
H A Dgeneric-phy.h2 * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
3 * Written by Jean-Jacques Hiblot <jjhiblot@ti.com>
5 * SPDX-License-Identifier: GPL-2.0+
11 #include <generic-phy-dp.h>
12 #include <generic-phy-mipi-dphy.h>
13 #include <generic-phy-pcie.h>
21 * union phy_configure_opts - Opaque generic phy configuration
24 * the MIPI_DPHY phy mode.
35 * struct phy_attrs - represents phy attributes
36 * @bus_width: Data path width implemented by PHY
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/OK3568_Linux_fs/kernel/drivers/phy/marvell/
H A Dphy-mvebu-a3700-comphy.c1 // SPDX-License-Identifier: GPL-2.0
9 * Structure inspired from phy-mvebu-cp110-comphy.c written by Antoine Tenart.
13 #include <linux/arm-smccc.h>
18 #include <linux/phy.h>
19 #include <linux/phy/phy.h>
50 #define COMPHY_FW_MODE(mode) ((mode) << 12) argument
51 #define COMPHY_FW_NET(mode, idx, speed) (COMPHY_FW_MODE(mode) | \ argument
54 #define COMPHY_FW_PCIE(mode, idx, speed, width) (COMPHY_FW_NET(mode, idx, speed) | \ argument
59 enum phy_mode mode; member
68 .mode = _mode, \
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/OK3568_Linux_fs/kernel/include/linux/phy/
H A Dphy.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * phy.h -- generic phy header file
5 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
19 #include <linux/phy/phy-dp.h>
20 #include <linux/phy/phy-mipi-dphy.h>
22 struct phy;
48 * union phy_configure_opts - Opaque generic phy configuration
51 * the MIPI_DPHY phy mode.
61 * struct phy_ops - set of function pointers for performing phy operations
62 * @init: operation to be performed for initializing phy
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/OK3568_Linux_fs/kernel/drivers/phy/hisilicon/
H A Dphy-histb-combphy.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2016-2017 HiSilicon Co., Ltd. http://www.hisilicon.com
17 #include <linux/phy/phy.h>
20 #include <dt-bindings/phy/phy.h>
48 struct phy *phy; member
49 struct histb_combphy_mode mode; member
55 void __iomem *reg = priv->mmio + COMBPHY_CFG_REG; in nano_register_write()
73 static int is_mode_fixed(struct histb_combphy_mode *mode) in is_mode_fixed() argument
75 return (mode->fixed != PHY_NONE) ? true : false; in is_mode_fixed()
80 struct histb_combphy_mode *mode = &priv->mode; in histb_combphy_set_mode() local
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/OK3568_Linux_fs/kernel/drivers/phy/ti/
H A Dphy-ti-pipe3.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * phy-ti-pipe3 - PIPE3 PHY driver.
5 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
12 #include <linux/phy/phy.h>
19 #include <linux/phy/omap_control_phy.h>
181 enum pipe3_mode mode; member
206 enum pipe3_mode mode; member
212 .mode = PIPE3_MODE_USBSS,
215 /* DRA75x TRM Table 26-17 Preferred USB3_PHY_RX SCP Register Settings */
238 .mode = PIPE3_MODE_SATA,
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/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/phy/
H A Dphy-hi3798cv200-combphy.txt1 HiSilicon STB PCIE/SATA/USB3 PHY
4 - compatible: Should be "hisilicon,hi3798cv200-combphy"
5 - reg: Should be the address space for COMBPHY configuration and state
8 - #phy-cells: Should be 1. The cell number is used to select the phy mode
9 as defined in <dt-bindings/phy/phy.h>.
10 - clocks: The phandle to clock provider and clock specifier pair.
11 - resets: The phandle to reset controller and reset specifier pair.
13 Refer to phy/phy-bindings.txt for the generic PHY binding properties.
16 - hisilicon,fixed-mode: If the phy device doesn't support mode select
17 but a fixed mode setting, the property should be present to specify
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H A Dti,phy-gmii-sel.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
4 ---
5 $id: "http://devicetree.org/schemas/phy/ti,phy-gmii-sel.yaml#"
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
8 title: CPSW Port's Interface Mode Selection PHY Tree Bindings
11 - Kishon Vijay Abraham I <kishon@ti.com>
16 The interface mode is selected by configuring the MII mode selection register(s)
20 +--------------+
21 +-------------------------------+ |SCM |
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/OK3568_Linux_fs/kernel/drivers/phy/amlogic/
H A Dphy-meson-axg-mipi-pcie-analog.c1 // SPDX-License-Identifier: GPL-2.0
3 * Amlogic AXG MIPI + PCIE analog PHY driver
8 #include <linux/phy/phy.h>
11 #include <dt-bindings/phy/phy.h>
34 #define HHI_MIPI_CNTL2_CH_EN(n) BIT(15 - (n))
38 struct phy *phy; member
39 unsigned int mode; member
50 static int phy_axg_mipi_pcie_analog_power_on(struct phy *phy) in phy_axg_mipi_pcie_analog_power_on() argument
52 struct phy_axg_mipi_pcie_analog_priv *priv = phy_get_drvdata(phy); in phy_axg_mipi_pcie_analog_power_on()
55 if (priv->mode != PHY_TYPE_PCIE) in phy_axg_mipi_pcie_analog_power_on()
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H A Dphy-meson-gxl-usb2.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Meson GXL and GXM USB2 PHY driver
15 #include <linux/phy/phy.h>
18 /* bits [31:27] are read-only */
66 /* bits [31:14] are read-only */
94 enum phy_mode mode; member
107 static int phy_meson_gxl_usb2_init(struct phy *phy) in phy_meson_gxl_usb2_init() argument
109 struct phy_meson_gxl_usb2_priv *priv = phy_get_drvdata(phy); in phy_meson_gxl_usb2_init()
112 ret = reset_control_reset(priv->reset); in phy_meson_gxl_usb2_init()
116 ret = clk_prepare_enable(priv->clk); in phy_meson_gxl_usb2_init()
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H A Dphy-meson-g12a-usb3-pcie.c1 // SPDX-License-Identifier: GPL-2.0
3 * Amlogic G12A USB3 + PCIE Combo PHY driver
15 #include <linux/phy/phy.h>
19 #include <dt-bindings/phy/phy.h>
60 struct phy *phy; member
61 unsigned int mode; member
79 regmap_write(priv->regmap, PHY_R4, reg); in phy_g12a_usb3_pcie_cr_bus_addr()
80 regmap_write(priv->regmap, PHY_R4, reg); in phy_g12a_usb3_pcie_cr_bus_addr()
82 regmap_write(priv->regmap, PHY_R4, reg | PHY_R4_PHY_CR_CAP_ADDR); in phy_g12a_usb3_pcie_cr_bus_addr()
84 ret = regmap_read_poll_timeout(priv->regmap, PHY_R5, val, in phy_g12a_usb3_pcie_cr_bus_addr()
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/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/net/dsa/
H A Dmt7530.txt6 - compatible: may be compatible = "mediatek,mt7530"
9 - #address-cells: Must be 1.
10 - #size-cells: Must be 0.
11 - mediatek,mcm: Boolean; if defined, indicates that either MT7530 is the part
12 on multi-chip module belong to MT7623A has or the remotely standalone
17 - core-supply: Phandle to the regulator node necessary for the core power.
18 - io-supply: Phandle to the regulator node necessary for the I/O power.
19 See Documentation/devicetree/bindings/regulator/mt6323-regulator.txt
24 - reset-gpios: Should be a gpio specifier for a reset line.
28 - resets : Phandle pointing to the system reset controller with
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H A Dsja1105.txt6 - compatible:
8 - "nxp,sja1105e"
9 - "nxp,sja1105t"
10 - "nxp,sja1105p"
11 - "nxp,sja1105q"
12 - "nxp,sja1105r"
13 - "nxp,sja1105s"
18 and the non-SGMII devices, while pin-compatible, are not equal in terms
24 - sja1105,role-mac:
25 - sja1105,role-phy:
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H A Dar9331.txt1 Atheros AR9331 built-in switch
4 It is a switch built-in to Atheros AR9331 WiSoC and addressable over internal
5 MDIO bus. All PHYs are built-in as well.
9 - compatible: should be: "qca,ar9331-switch"
10 - reg: Address on the MII bus for the switch.
11 - resets : Must contain an entry for each entry in reset-names.
12 - reset-names : Must include the following entries: "switch"
13 - interrupt-parent: Phandle to the parent interrupt controller
14 - interrupts: IRQ line for the switch
15 - interrupt-controller: Indicates the switch is itself an interrupt
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/OK3568_Linux_fs/kernel/drivers/gpu/drm/hisilicon/kirin/kirin960/
H A Ddw_drm_dsi.c1 // SPDX-License-Identifier: GPL-2.0-only
6 * Copyright (c) 2014-2016 Hisilicon Limited.
39 #define DTS_COMP_DSI_NAME "hisilicon,hi3660-dsi"
40 #define DSS_REDUCE(x) ((x) > 0 ? ((x) - 1) : (x))
61 u32 mask = (1UL << bw) - 1UL; in set_reg()
72 const struct drm_display_mode *mode) in dsi_encoder_phy_mode_valid() argument
80 DRM_DEBUG_DRIVER("Checking mode %ix%i@%i clock: %i...", mode->hdisplay, in dsi_encoder_phy_mode_valid()
81 mode->vdisplay, drm_mode_vrefresh(mode), mode->clock); in dsi_encoder_phy_mode_valid()
82 if ((mode->hdisplay == 1920 && mode->vdisplay == 1080 && mode->clock == 148500) || in dsi_encoder_phy_mode_valid()
83 (mode->hdisplay == 1920 && mode->vdisplay == 1080 && mode->clock == 80192) || in dsi_encoder_phy_mode_valid()
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/OK3568_Linux_fs/kernel/arch/powerpc/boot/dts/fsl/
H A Dt1040rdb.dts4 * Copyright 2014 - 2015 Freescale Semiconductor Inc.
35 /include/ "t104xsi-pre.dtsi"
49 fixed-link = <0 1 1000 0 0>;
50 phy-connection-type = "sgmii";
54 fixed-link = <1 1 1000 0 0>;
55 phy-connection-type = "sgmii";
59 phy-handle = <&phy_sgmii_2>;
60 phy-connection-type = "sgmii";
64 phy_sgmii_2: ethernet-phy@3 {
68 /* VSC8514 QSGMII PHY */
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/OK3568_Linux_fs/u-boot/drivers/phy/
H A Dphy-uclass.c2 * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
3 * Written by Jean-Jacques Hiblot <jjhiblot@ti.com>
5 * SPDX-License-Identifier: GPL-2.0+
10 #include <generic-phy.h>
16 return (struct phy_ops *)dev->driver->ops; in phy_dev_ops()
19 static int generic_phy_xlate_offs_flags(struct phy *phy, in generic_phy_xlate_offs_flags() argument
22 debug("%s(phy=%p)\n", __func__, phy); in generic_phy_xlate_offs_flags()
24 if (args->args_count > 1) { in generic_phy_xlate_offs_flags()
25 debug("Invaild args_count: %d\n", args->args_count); in generic_phy_xlate_offs_flags()
26 return -EINVAL; in generic_phy_xlate_offs_flags()
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/OK3568_Linux_fs/kernel/drivers/usb/phy/
H A Dphy-ab8500-usb.c1 // SPDX-License-Identifier: GPL-2.0+
5 * Copyright (C) 2010-2013 ST-Ericsson AB
22 #include <linux/usb/musb-ux500.h>
121 /* Driver is using the ab-iddet driver*/
127 struct usb_phy phy; member
132 enum ab8500_usb_mode mode; member
147 return container_of(x, struct ab8500_usb, phy); in phy_to_ab()
152 abx500_set_register_interruptible(ab->dev, in ab8500_usb_wd_workaround()
159 abx500_set_register_interruptible(ab->dev, in ab8500_usb_wd_workaround()
167 abx500_set_register_interruptible(ab->dev, in ab8500_usb_wd_workaround()
[all …]
/OK3568_Linux_fs/kernel/drivers/net/
H A Dsungem_phy.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * PHY drivers for the sungem ethernet driver.
7 * (c) 2002-2007, Benjamin Herrenscmidt (benh@kernel.crashing.org)
10 * - Add support for PHYs that provide an IRQ line
11 * - Eventually moved the entire polling state machine in
14 * - On LXT971 & BCM5201, Apple uses some chip specific regs
17 * - Apple has some additional power management code for some
39 /* Link modes of the BCM5400 PHY */
51 static inline int __sungem_phy_read(struct mii_phy* phy, int id, int reg) in __sungem_phy_read() argument
53 return phy->mdio_read(phy->dev, id, reg); in __sungem_phy_read()
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/OK3568_Linux_fs/kernel/drivers/media/platform/omap3isp/
H A Dispcsiphy.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * TI OMAP3 ISP - CSI PHY module
23 static void csiphy_routing_cfg_3630(struct isp_csiphy *phy, in csiphy_routing_cfg_3630() argument
28 u32 shift, mode; in csiphy_routing_cfg_3630() local
30 regmap_read(phy->isp->syscon, phy->isp->syscon_offset, &reg); in csiphy_routing_cfg_3630()
41 mode = OMAP3630_CONTROL_CAMERA_PHY_CTRL_CAMMODE_DPHY; in csiphy_routing_cfg_3630()
49 mode = OMAP3630_CONTROL_CAMERA_PHY_CTRL_CAMMODE_DPHY; in csiphy_routing_cfg_3630()
53 /* Select data/clock or data/strobe mode for CCP2 */ in csiphy_routing_cfg_3630()
57 mode = OMAP3630_CONTROL_CAMERA_PHY_CTRL_CAMMODE_CCP2_DATA_STROBE; in csiphy_routing_cfg_3630()
59 mode = OMAP3630_CONTROL_CAMERA_PHY_CTRL_CAMMODE_CCP2_DATA_CLOCK; in csiphy_routing_cfg_3630()
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/OK3568_Linux_fs/kernel/drivers/phy/st/
H A Dphy-spear1340-miphy.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * ST spear1340-miphy driver
12 #include <linux/dma-mapping.h>
17 #include <linux/phy/phy.h>
32 /* PCIE - SATA configuration registers */
80 /* phy mode: 0 for SATA 1 for PCIe */
81 enum spear1340_miphy_mode mode; member
84 /* phy struct pointer */
85 struct phy *phy; member
90 regmap_update_bits(priv->misc, SPEAR1340_PCIE_SATA_CFG, in spear1340_miphy_sata_init()
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/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/net/
H A Dti,dp83822.yaml1 # SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
4 ---
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
8 title: TI DP83822 ethernet PHY
11 - Dan Murphy <dmurphy@ti.com>
14 The DP83822 is a low-power, single-port, 10/100 Mbps Ethernet PHY. It
16 data over standard, twisted-pair cables or to connect to an external,
17 fiber-optic transceiver. Additionally, the DP83822 provides flexibility to
20 Specifications about the Ethernet PHY can be found at:
24 - $ref: "ethernet-phy.yaml#"
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/OK3568_Linux_fs/kernel/drivers/mmc/host/
H A Dsdhci-xenon-phy.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * PHY support for Xenon SDHC
8 * Date: 2016-8-24
16 #include "sdhci-pltfm.h"
17 #include "sdhci-xenon.h"
19 /* Register base for eMMC PHY 5.0 Version */
21 /* Register base for eMMC PHY 5.1 Version */
113 * List offset of PHY registers and some special register values
114 * in eMMC PHY 5.0 or eMMC PHY 5.1
136 "emmc 5.0 phy",
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/OK3568_Linux_fs/kernel/arch/arm/boot/dts/
H A Dls1021a-tsn.dts1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright 2016-2018 NXP Semiconductors
6 /dts-v1/;
10 model = "NXP LS1021A-TSN Board";
12 sys_mclk: clock-mclk {
13 compatible = "fixed-clock";
14 #clock-cells = <0>;
15 clock-frequency = <24576000>;
18 reg_vdda_codec: regulator-3V3 {
19 compatible = "regulator-fixed";
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