bindings/phy/ti%2Cphy-gmii-sel.yaml

1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
4 ---
5 $id: "http://devicetree.org/schemas/phy/ti,phy-gmii-sel.yaml#"
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
8 title: CPSW Port's Interface Mode Selection PHY Tree Bindings
11   - Kishon Vijay Abraham I <kishon@ti.com>
16   The interface mode is selected by configuring the MII mode selection register(s)
20                                                +--------------+
21         +-------------------------------+      |SCM           |
22         |                     CPSW      |      |  +---------+ |
23         |        +--------------------------------+gmii_sel | |
24         |        |                      |      |  +---------+ |
25         |   +----v---+     +--------+   |      +--------------+
26         |   |Port 1..<--+-->GMII/MII<------->
28         |   +--------+  |  +--------+   |
30         |               |  +--------+   |
31         |               |  | RMII   <------->
32         |               +-->        |   |
33         |               |  +--------+   |
35         |               |  +--------+   |
36         |               |  | RGMII  <------->
37         |               +-->        |   |
38         |                  +--------+   |
39         +-------------------------------+
41   CPSW Port's Interface Mode Selection PHY describes MII interface mode between
42   CPSW Port and Ethernet PHY which depends on Eth PHY and board configuration.
44   CPSW Port's Interface Mode Selection PHY device should defined as child device
46   PHY bindings.
51       - ti,am3352-phy-gmii-sel
52       - ti,dra7xx-phy-gmii-sel
53       - ti,am43xx-phy-gmii-sel
54       - ti,dm814-phy-gmii-sel
55       - ti,am654-phy-gmii-sel
60   '#phy-cells': true
63   - if:
68               - ti,dra7xx-phy-gmii-sel
69               - ti,dm814-phy-gmii-sel
70               - ti,am654-phy-gmii-sel
73         '#phy-cells':
76   - if:
81               - ti,am3352-phy-gmii-sel
82               - ti,am43xx-phy-gmii-sel
85         '#phy-cells':
88             - CPSW port number (starting from 1)
89             - RMII refclk mode
92   - compatible
93   - reg
94   - '#phy-cells'
99   - |
100     phy_gmii_sel: phy-gmii-sel@650 {
101         compatible = "ti,am3352-phy-gmii-sel";
103         #phy-cells = <2>;