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/OK3568_Linux_fs/u-boot/drivers/mtd/nand/raw/
H A Domap_gpmc.c2 * (C) Copyright 2004-2008 Texas Instruments, <www.ti.com>
5 * SPDX-License-Identifier: GPL-2.0+
16 #include <nand.h>
55 * omap_nand_hwcontrol - Set the address pointers corretly for the
63 int cs = info->cs; in omap_nand_hwcontrol()
71 this->IO_ADDR_W = (void __iomem *)&gpmc_cfg->cs[cs].nand_cmd; in omap_nand_hwcontrol()
74 this->IO_ADDR_W = (void __iomem *)&gpmc_cfg->cs[cs].nand_adr; in omap_nand_hwcontrol()
77 this->IO_ADDR_W = (void __iomem *)&gpmc_cfg->cs[cs].nand_dat; in omap_nand_hwcontrol()
82 writeb(cmd, this->IO_ADDR_W); in omap_nand_hwcontrol()
90 return gpmc_cfg->status & (1 << (8 + info->ws)); in omap_dev_ready()
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H A Dsunxi_nand.c6 * https://github.com/yuq/sunxi-nfc-mtd
9 * https://github.com/hno/Allwinner-Info
25 * SPDX-License-Identifier: GPL-2.0+
31 #include <nand.h>
79 #define NFC_PAGE_SHIFT(x) (((x) < 10 ? 0 : (x) - 10) << 8)
115 #define NFC_ADR_NUM(x) (((x) - 1) << 16)
172 * @RB_NATIVE: use sunxi NAND controller Ready/Busy support. The Ready/Busy
173 * pin of the NAND flash chip must be connected to one of the
174 * native NAND R/B pins (those which can be muxed to the NAND
177 * pin of the NAND flash chip must be connected to a GPIO capable
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H A Dlpc32xx_nand_mlc.c2 * LPC32xx MLC NAND flash controller driver
7 * SPDX-License-Identifier: GPL-2.0+
11 * The MLC NAND flash controller provides hardware Reed-Solomon ECC
12 * covering in- and out-of-band data together. Therefore, in- and out-
13 * of-band data must be written together in order to have a valid ECC.
15 * Consequently, pages with meaningful in-band data are written with
16 * blank (all-ones) out-of-band data and a valid ECC, and any later
17 * out-of-band data write will void the ECC.
19 * Therefore, code which reads such late-written out-of-band data
20 * should not rely on the ECC validity.
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H A Dfsmc_nand.c8 * SPDX-License-Identifier: GPL-2.0+
12 #include <nand.h>
25 * ECC4 and ECC1 have 13 bytes and 3 bytes of ecc respectively for 512 bytes of
62 * ECC4 layout for NAND of pagesize 4096 bytes & OOBsize 224 bytes. 13*8 bytes
63 * of OOB size is reserved for ECC, Byte no. 0 & 1 reserved for bad block & 118
98 * ECC placement definitions in oobfree type format
99 * There are 13 bytes of ecc for every 512 byte block and it has to be read
102 * Managing the ecc bytes in the following way makes it easier for software to
103 * read ecc bytes consecutive to data bytes. This way is similar to
104 * oobfree structure maintained already in u-boot nand driver
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H A Datmel_nand.c2 * (C) Copyright 2007-2008
8 * Add Programmable Multibit ECC support for various AT91 SoC
11 * SPDX-License-Identifier: GPL-2.0+
19 #include <nand.h>
31 #include "atmel_nand_ecc.h" /* Hardware ECC registers */
72 * Return number of ecc bytes per sector according to sector size and
78 * 2-bits 4-bytes 4-bytes
79 * 4-bits 7-bytes 7-bytes
80 * 8-bits 13-bytes 14-bytes
81 * 12-bits 20-bytes 21-bytes
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H A Ddavinci_nand.c2 * NAND driver for TI DaVinci based boards.
6 * Based on Linux DaVinci NAND driver by TI. Original copyright follows:
11 * linux/drivers/mtd/nand/raw/nand_davinci.c
13 * NAND Flash Driver
17 * ----------------------------------------------------------------------------
19 * SPDX-License-Identifier: GPL-2.0+
21 * ----------------------------------------------------------------------------
24 * This is a device driver for the NAND flash device found on the
29 -
34 #include <nand.h>
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H A Dnand_base.c3 * This is the generic MTD driver for NAND flash devices. It should be
4 * capable of working with almost all NAND chips currently available.
7 * http://www.linux-mtd.infradead.org/doc/nand.html
10 * 2002-2006 Thomas Gleixner (tglx@linutronix.de)
20 * Check, if mtd->ecctype should be set to MTD_ECC_HW
21 * if we have HW ECC support.
113 if (ofs & ((1ULL << chip->phys_erase_shift) - 1)) { in check_offs_len()
115 ret = -EINVAL; in check_offs_len()
119 if (len & ((1ULL << chip->phys_erase_shift) - 1)) { in check_offs_len()
121 ret = -EINVAL; in check_offs_len()
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H A DKconfig2 menuconfig NAND config
3 bool "Raw NAND Device Support"
4 if NAND
9 This option, if enabled, provides more flexible and linux-like
10 NAND initialization process.
15 Omit standard ECC layouts to safe space. Select this if your driver
16 is known to provide its own ECC layout.
19 bool "Support Atmel NAND controller"
22 Enable this driver for NAND flash platforms using an Atmel NAND
28 bool "Atmel Hardware ECC"
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/OK3568_Linux_fs/u-boot/arch/arm/mach-uniphier/boot-device/
H A Dboot-device-ld11.c2 * Copyright (C) 2016-2017 Socionext Inc.
5 * SPDX-License-Identifier: GPL-2.0+
13 #include "boot-device.h"
16 {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 128KB, Addr 4)"},
17 {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 128KB, Addr 4)"},
18 {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 128KB, Addr 5)"},
19 {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 128KB, Addr 5)"},
20 {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 256KB, Addr 5)"},
21 {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 256KB, Addr 5)"},
22 {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 512KB, Addr 5)"},
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H A Dboot-device-pxs2.c2 * Copyright (C) 2015-2017 Socionext Inc.
5 * SPDX-License-Identifier: GPL-2.0+
13 #include "boot-device.h"
16 {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 128KB, Addr 4)"},
17 {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 128KB, Addr 5)"},
18 {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 128KB, Addr 5)"},
19 {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 256KB, Addr 5)"},
20 {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 256KB, Addr 5)"},
21 {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 512KB, Addr 5)"},
22 {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 512KB, Addr 5)"},
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/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/mtd/
H A Ddavinci-nand.txt1 Device tree bindings for Texas instruments Davinci/Keystone NAND controller
4 NAND interface contains.
7 Davinci DM646x - https://www.ti.com/lit/ug/sprueq7c/sprueq7c.pdf
8 Kestone - https://www.ti.com/lit/ug/sprugz3a/sprugz3a.pdf
12 - compatible: "ti,davinci-nand"
13 "ti,keystone-nand"
15 - reg: Contains 2 offset/length values:
16 - offset and length for the access window.
17 - offset and length for accessing the AEMIF
20 - ti,davinci-chipselect: number of chipselect. Indicates on the
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H A Dnvidia-tegra20-nand.txt1 NVIDIA Tegra NAND Flash controller
4 - compatible: Must be one of:
5 - "nvidia,tegra20-nand"
6 - reg: MMIO address range
7 - interrupts: interrupt output of the NFC controller
8 - clocks: Must contain an entry for each entry in clock-names.
9 See ../clocks/clock-bindings.txt for details.
10 - clock-names: Must include the following entries:
11 - nand
12 - resets: Must contain an entry for each entry in reset-names.
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H A Dhisi504-nand.txt1 Hisilicon Hip04 Soc NAND controller DT binding
5 - compatible: Should be "hisilicon,504-nfc".
6 - reg: The first contains base physical address and size of
7 NAND controller's registers. The second contains base
8 physical address and size of NAND controller's buffer.
9 - interrupts: Interrupt number for nfc.
10 - nand-bus-width: See nand-controller.yaml.
11 - nand-ecc-mode: Support none and hw ecc mode.
12 - #address-cells: Partition address, should be set 1.
13 - #size-cells: Partition size, should be set 1.
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H A Dgpmc-nand.txt3 GPMC connected NAND (found on OMAP boards) are represented as child nodes of
4 the GPMC controller with a name of "nand".
7 explained in a separate documents - please refer to
8 Documentation/devicetree/bindings/memory-controllers/omap-gpmc.txt
10 For NAND specific properties such as ECC modes or bus width, please refer to
11 Documentation/devicetree/bindings/mtd/nand-controller.yaml
16 - compatible: "ti,omap2-nand"
17 - reg: range id (CS number), base offset and length of the
18 NAND I/O space
19 - interrupts: Two interrupt specifiers, one for fifoevent, one for termcount.
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H A Dmtk-nand.txt1 MTK SoCs NAND FLASH controller (NFC) DT binding
3 This file documents the device tree bindings for MTK SoCs NAND controllers.
5 the nand controller interface driver and the ECC engine driver.
10 1) NFC NAND Controller Interface (NFI):
13 The first part of NFC is NAND Controller Interface (NFI) HW.
15 - compatible: Should be one of
16 "mediatek,mt2701-nfc",
17 "mediatek,mt2712-nfc",
18 "mediatek,mt7622-nfc".
19 - reg: Base physical address and size of NFI.
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H A Dmarvell-nand.txt1 Marvell NAND Flash Controller (NFC)
4 - compatible: can be one of the following:
5 * "marvell,armada-8k-nand-controller"
6 * "marvell,armada370-nand-controller"
7 * "marvell,pxa3xx-nand-controller"
8 * "marvell,armada-8k-nand" (deprecated)
9 * "marvell,armada370-nand" (deprecated)
10 * "marvell,pxa3xx-nand" (deprecated)
13 - reg: NAND flash controller memory area.
14 - #address-cells: shall be set to 1. Encode the NAND CS.
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H A Datmel-nand.txt1 Atmel NAND flash controller bindings
3 The NAND flash controller node should be defined under the EBI bus (see
4 Documentation/devicetree/bindings/memory-controllers/atmel,ebi.txt).
5 One or several NAND devices can be defined under this NAND controller.
6 The NAND controller might be connected to an ECC engine.
8 * NAND controller bindings:
11 - compatible: should be one of the following
12 "atmel,at91rm9200-nand-controller"
13 "atmel,at91sam9260-nand-controller"
14 "atmel,at91sam9261-nand-controller"
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H A Dnand-controller.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mtd/nand-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NAND Chip and NAND Controller Generic Binding
10 - Miquel Raynal <miquel.raynal@bootlin.com>
11 - Richard Weinberger <richard@nod.at>
14 The NAND controller should be represented with its own DT node, and
15 all NAND chips attached to this controller should be defined as
16 children nodes of the NAND controller. This representation should be
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H A Drockchip,nand-controller.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mtd/rockchip,nand-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip SoCs NAND FLASH Controller (NFC)
10 - $ref: "nand-controller.yaml#"
13 - Heiko Stuebner <heiko@sntech.de>
18 - const: rockchip,px30-nfc
19 - const: rockchip,rk2928-nfc
20 - const: rockchip,rv1108-nfc
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H A Dvf610-nfc.txt1 Freescale's NAND flash controller (NFC)
3 This variant of the Freescale NAND flash controller (NFC) can be found on
7 - compatible: Should be set to "fsl,vf610-nfc".
8 - reg: address range of the NFC.
9 - interrupts: interrupt of the NFC.
10 - #address-cells: shall be set to 1. Encode the nand CS.
11 - #size-cells : shall be set to 0.
12 - assigned-clocks: main clock from the SoC, for Vybrid <&clks VF610_CLK_NFC>;
13 - assigned-clock-rates: The NAND bus timing is derived from this clock
14 rate and should not exceed maximum timing for any NAND memory chip
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/OK3568_Linux_fs/kernel/drivers/mtd/nand/raw/
H A Dfsmc_nand.c1 // SPDX-License-Identifier: GPL-2.0
5 * Driver for NAND portions
11 * Based on drivers/mtd/nand/nomadik_nand.c (removed in v3.8)
20 #include <linux/dma-direction.h>
21 #include <linux/dma-mapping.h>
37 #include <mtd/mtd-abi.h>
61 /* fsmc controller registers for NAND flash */
99 * TOUDEL = 7ns (Output delay from the flip-flops to the board)
120 * struct fsmc_nand_data - structure for FSMC NAND device state
124 * @nand: Chip related info for a NAND flash.
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H A Dsunxi_nand.c1 // SPDX-License-Identifier: GPL-2.0+
6 * https://github.com/yuq/sunxi-nfc-mtd
9 * https://github.com/hno/Allwinner-Info
16 #include <linux/dma-mapping.h>
70 #define NFC_PAGE_SHIFT(x) (((x) < 10 ? 0 : (x) - 10) << 8)
107 #define NFC_ADR_NUM(x) (((x) - 1) << 16)
161 * struct sunxi_nand_chip_sel - stores information related to NAND Chip Select
163 * @cs: the NAND CS id used to communicate with a NAND Chip
164 * @rb: the Ready/Busy pin ID. -1 means no R/B pin connected to the NFC
172 * struct sunxi_nand_hw_ecc - stores information related to HW ECC support
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H A Domap2.c1 // SPDX-License-Identifier: GPL-2.0-only
10 #include <linux/dma-mapping.h>
20 #include <linux/omap-dma.h>
29 #include <linux/omap-gpmc.h>
30 #include <linux/platform_data/mtd-nand-omap2.h>
32 #define DRIVER_NAME "omap2-nand"
122 /* GPMC ecc engine settings for read */
123 #define BCH_WRAPMODE_1 1 /* BCH wrap mode 1 */
129 /* GPMC ecc engine settings for write */
130 #define BCH_WRAPMODE_6 6 /* BCH wrap mode 6 */
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H A Dnand_base.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * This is the generic MTD driver for NAND flash devices. It should be
5 * capable of working with almost all NAND chips currently available.
8 * http://www.linux-mtd.infradead.org/doc/nand.html
11 * 2002-2006 Thomas Gleixner (tglx@linutronix.de)
21 * Check, if mtd->ecctype should be set to MTD_ECC_HW
22 * if we have HW ECC support.
37 #include <linux/mtd/nand.h>
52 int lastpage = (mtd->erasesize / mtd->writesize) - 1; in nand_pairing_dist3_get_info()
59 info->group = 0; in nand_pairing_dist3_get_info()
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/OK3568_Linux_fs/u-boot/include/linux/mtd/
H A Drawnand.h2 * Copyright © 2000-2010 David Woodhouse <dwmw2@infradead.org>
6 * SPDX-License-Identifier: GPL-2.0+
9 * Contains standard defines and IDs for NAND flash devices
35 /* Scan and identify a NAND device */
39 * and override command or ECC setup according to flash type.
45 /* Free resources held by the NAND device */
77 * Standard NAND flash commands
104 /* Extended commands for AG-AND device */
115 /* multi-bank error status (banks 0-3) */
123 #define NAND_CMD_NONE -1
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