1*4882a593SmuzhiyunDevice tree bindings for Texas instruments Davinci/Keystone NAND controller 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunThis file provides information, what the device node for the davinci/keystone 4*4882a593SmuzhiyunNAND interface contains. 5*4882a593Smuzhiyun 6*4882a593SmuzhiyunDocumentation: 7*4882a593SmuzhiyunDavinci DM646x - https://www.ti.com/lit/ug/sprueq7c/sprueq7c.pdf 8*4882a593SmuzhiyunKestone - https://www.ti.com/lit/ug/sprugz3a/sprugz3a.pdf 9*4882a593Smuzhiyun 10*4882a593SmuzhiyunRequired properties: 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun- compatible: "ti,davinci-nand" 13*4882a593Smuzhiyun "ti,keystone-nand" 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun- reg: Contains 2 offset/length values: 16*4882a593Smuzhiyun - offset and length for the access window. 17*4882a593Smuzhiyun - offset and length for accessing the AEMIF 18*4882a593Smuzhiyun control registers. 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun- ti,davinci-chipselect: number of chipselect. Indicates on the 21*4882a593Smuzhiyun davinci_nand driver which chipselect is used 22*4882a593Smuzhiyun for accessing the nand. 23*4882a593Smuzhiyun Can be in the range [0-3]. 24*4882a593Smuzhiyun 25*4882a593SmuzhiyunRecommended properties : 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun- ti,davinci-mask-ale: mask for ALE. Needed for executing address 28*4882a593Smuzhiyun phase. These offset will be added to the base 29*4882a593Smuzhiyun address for the chip select space the NAND Flash 30*4882a593Smuzhiyun device is connected to. 31*4882a593Smuzhiyun If not set equal to 0x08. 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun- ti,davinci-mask-cle: mask for CLE. Needed for executing command 34*4882a593Smuzhiyun phase. These offset will be added to the base 35*4882a593Smuzhiyun address for the chip select space the NAND Flash 36*4882a593Smuzhiyun device is connected to. 37*4882a593Smuzhiyun If not set equal to 0x10. 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun- ti,davinci-mask-chipsel: mask for chipselect address. Needed to mask 40*4882a593Smuzhiyun addresses for given chipselect. 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun- nand-ecc-mode: operation mode of the NAND ecc mode. ECC mode 43*4882a593Smuzhiyun valid values for davinci driver: 44*4882a593Smuzhiyun - "none" 45*4882a593Smuzhiyun - "soft" 46*4882a593Smuzhiyun - "hw" 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun- ti,davinci-ecc-bits: used ECC bits, currently supported 1 or 4. 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun- nand-bus-width: buswidth 8 or 16. If not present 8. 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun- nand-on-flash-bbt: use flash based bad block table support. OOB 53*4882a593Smuzhiyun identifier is saved in OOB area. If not present 54*4882a593Smuzhiyun false. 55*4882a593Smuzhiyun 56*4882a593SmuzhiyunDeprecated properties: 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun- ti,davinci-ecc-mode: operation mode of the NAND ecc mode. ECC mode 59*4882a593Smuzhiyun valid values for davinci driver: 60*4882a593Smuzhiyun - "none" 61*4882a593Smuzhiyun - "soft" 62*4882a593Smuzhiyun - "hw" 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun- ti,davinci-nand-buswidth: buswidth 8 or 16. If not present 8. 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun- ti,davinci-nand-use-bbt: use flash based bad block table support. OOB 67*4882a593Smuzhiyun identifier is saved in OOB area. If not present 68*4882a593Smuzhiyun false. 69*4882a593Smuzhiyun 70*4882a593SmuzhiyunNand device bindings may contain additional sub-nodes describing partitions of 71*4882a593Smuzhiyunthe address space. See partition.txt for more detail. The NAND Flash timing 72*4882a593Smuzhiyunvalues must be programmed in the chip select’s node of AEMIF 73*4882a593Smuzhiyunmemory-controller (see Documentation/devicetree/bindings/memory-controllers/ 74*4882a593Smuzhiyundavinci-aemif.txt). 75*4882a593Smuzhiyun 76*4882a593SmuzhiyunExample(da850 EVM ): 77*4882a593Smuzhiyun 78*4882a593Smuzhiyunnand_cs3@62000000 { 79*4882a593Smuzhiyun compatible = "ti,davinci-nand"; 80*4882a593Smuzhiyun reg = <0x62000000 0x807ff 81*4882a593Smuzhiyun 0x68000000 0x8000>; 82*4882a593Smuzhiyun ti,davinci-chipselect = <1>; 83*4882a593Smuzhiyun ti,davinci-mask-ale = <0>; 84*4882a593Smuzhiyun ti,davinci-mask-cle = <0>; 85*4882a593Smuzhiyun ti,davinci-mask-chipsel = <0>; 86*4882a593Smuzhiyun nand-ecc-mode = "hw"; 87*4882a593Smuzhiyun ti,davinci-ecc-bits = <4>; 88*4882a593Smuzhiyun nand-on-flash-bbt; 89*4882a593Smuzhiyun 90*4882a593Smuzhiyun partition@180000 { 91*4882a593Smuzhiyun label = "ubifs"; 92*4882a593Smuzhiyun reg = <0x180000 0x7e80000>; 93*4882a593Smuzhiyun }; 94*4882a593Smuzhiyun}; 95