2  *  Copyright © 2000-2010 David Woodhouse <dwmw2@infradead.org>
6  * SPDX-License-Identifier:	GPL-2.0+
9  *	Contains standard defines and IDs for NAND flash devices
35 /* Scan and identify a NAND device */
39  * and override command or ECC setup according to flash type.
45 /* Free resources held by the NAND device */
77  * Standard NAND flash commands
104 /* Extended commands for AG-AND device */
115 /* multi-bank error status (banks 0-3) */
123 #define NAND_CMD_NONE		-1
132 #define NAND_DATA_IFACE_CHECK_ONLY	-1
147  * Constants for Hardware ECC
149 /* Reset Hardware ECC for read */
151 /* Reset Hardware ECC for write */
153 /* Enable Hardware ECC before syndrome is read back from flash */
157  * Enable generic NAND 'page erased' check. This check is only done when
158  * ecc.correct() returns -EBADMSG.
165  * If your controller already sends the required NAND commands when
188  * Chip requires ready check on read (for auto-incremented sequential read).
197 /* Device is one of 'new' xD cards that expose fake nand command set */
200 /* Device behaves just like nand, but is readonly */
219 #define NAND_HAS_CACHEPROG(chip) ((chip->options & NAND_CACHEPRG))
220 #define NAND_HAS_SUBPAGE_READ(chip) ((chip->options & NAND_SUBPAGE_READ))
221 #define NAND_HAS_SUBPAGE_WRITE(chip) !((chip)->options & NAND_NO_SUBPAGE_WRITE)
228  * (e.g. because it needs them DMA-coherent).
234  * Autodetect nand buswidth with readid/onfi.
235  * This suppose the driver will configure the hardware in 8 bits mode
246 /* Options set by nand scan */
249 /* Nand scan has allocated controller struct */
261 /* ONFI timing mode, used in both asynchronous and synchronous mode */
273 /* Vendor-specific feature address (Micron) */
350 /* Extended ECC information Block Definition (since ONFI 2.1) */
361 #define ONFI_SECTION_TYPE_2	2	/* for ECC information. */
465 	/* ECC and endurance block */
483 …* struct nand_hw_control - Control structure for hardware controller (e.g ECC generator) shared am…
486  * @wq:			wait queue to sleep on if a NAND operation is in
496  * struct nand_ecc_step_info - ECC step information of ECC engine
497  * @stepsize: data bytes per ECC step
508  * struct nand_ecc_caps - capability of ECC engine
509  * @stepinfos: array of ECC step information
510  * @nstepinfos: number of ECC step information
511  * @calc_ecc_bytes: driver's hook to calculate ECC bytes per step
520  * struct nand_ecc_ctrl - Control structure for ECC
521  * @mode:	ECC mode
522  * @steps:	number of ECC steps per page
523  * @size:	data bytes per ECC step
524  * @bytes:	ECC bytes per step
525  * @strength:	max number of correctible bits per ECC step
526  * @total:	total number of ECC bytes per page
527  * @prepad:	padding information for syndrome based ECC generators
528  * @postpad:	padding information for syndrome based ECC generators
529  * @options:	ECC specific options (see NAND_ECC_XXX flags defined above)
530  * @layout:	ECC layout control struct pointer
531  * @priv:	pointer to private ECC control data
532  * @hwctl:	function to control hardware ECC generator. Must only
533  *		be provided if an hardware ECC is available
534  * @calculate:	function for ECC calculation or readback from ECC hardware
535  * @correct:	function for ECC correction, matching to ECC generator (sw/hw).
537  *		corrected bitflips, -EBADMSG if the number of bitflips exceed
538  *		ECC strength, or any other error code if the error is not
540  *		If -EBADMSG is returned the input buffers should be left
542  * @read_page_raw:	function to read a raw page without ECC. This function
543  *			should hide the specific layout used by the ECC
544  *			controller and always return contiguous in-band and
545  *			out-of-band data even if they're not stored
546  *			contiguously on the NAND chip (e.g.
547  *			NAND_ECC_HW_SYNDROME interleaves in-band and
548  *			out-of-band data).
549  * @write_page_raw:	function to write a raw page without ECC. This function
550  *			should hide the specific layout used by the ECC
552  *			in-band and out-of-band data. ECC controller is
555  *			NAND_ECC_HW_SYNDROME interleaves in-band and
556  *			out-of-band data).
557  * @read_page:	function to read a page according to the ECC generator
559  *		any single ECC step, 0 if bitflips uncorrectable, -EIO hw error
560  * @read_subpage:	function to read parts of the page covered by ECC;
562  * @write_subpage:	function to write parts of the page covered by ECC.
563  * @write_page:	function to write a page according to the ECC generator
565  * @write_oob_raw:	function to write chip OOB data without ECC
566  * @read_oob_raw:	function to read chip OOB data without ECC
571 	nand_ecc_modes_t mode;  member
582 	void (*hwctl)(struct mtd_info *mtd, int mode);
609 static inline int nand_standard_page_accessors(struct nand_ecc_ctrl *ecc)  in nand_standard_page_accessors()  argument
611 	return !(ecc->options & NAND_ECC_CUSTOM_PAGE_ACCESS);  in nand_standard_page_accessors()
615  * struct nand_buffers - buffer structure for read/write
616  * @ecccalc:	buffer pointer for calculated ECC, size is oobsize.
617  * @ecccode:	buffer pointer for ECC read from flash, size is oobsize.
631  * struct nand_sdr_timings - SDR NAND chip timings
633  * This struct defines the timing requirements of a SDR NAND chip.
634  * These information can be found in every NAND datasheets and the timings
652  * @tCHZ_max: CE# high to output hi-Z
661  * @tIR_min: Output hi-Z to RE# low
662  * @tITC_max: Interface and Timing Mode Change time
668  * @tRHZ_max: RE# high to output hi-Z
723  * enum nand_data_interface_type - NAND interface timing type
731  * struct nand_data_interface - NAND interface timing
743  * nand_get_sdr_timings - get SDR timing from data interface
749 	if (conf->type != NAND_SDR_IFACE)  in nand_get_sdr_timings()
750 		return ERR_PTR(-EINVAL);  in nand_get_sdr_timings()
752 	return &conf->timings.sdr;  in nand_get_sdr_timings()
756  * struct nand_chip - NAND Private Flash Chip Data
783  *			setting the read-retry mode. Mostly needed for MLC NAND.
784  * @ecc:		[BOARDSPECIFIC] ECC control structure
787  * @hwcontrol:		platform-specific hardware control structure
792  * @state:		[INTERN] the current state of the NAND device
812  * @ecc_strength_ds:	[INTERN] ECC correctability from the datasheet.
815  * @ecc_step_ds:	[INTERN] ECC step required by the @ecc_strength_ds,
816  *                      also from the datasheet. It is the recommended ECC step
818  * @onfi_timing_mode_default: [INTERN] default ONFI timing mode. This field is
819  *			      set to the actually used ONFI mode if the chip is
821  *			      the NAND chip is not ONFI compliant.
824  * @pagemask:		[INTERN] page number mask = number of (pages / chip) - 1
839  * @onfi_set_features:	[REPLACEABLE] set the features for ONFI nand
840  * @onfi_get_features:	[REPLACEABLE] get the features for ONFI nand
855  * @write_page:		[REPLACEABLE] High-level page write function
930 	struct nand_ecc_ctrl ecc;  member
951 	return &chip->mtd;  in nand_to_mtd()
956 	return chip->priv;  in nand_get_controller_data()
961 	chip->priv = priv;  in nand_set_controller_data()
965  * NAND Flash Manufacturer ID Codes
982 /* The maximum expected count of bytes in the NAND ID sequence */
986  * A helper for defining older NAND chips where the second ID byte fully
988  * size). All these chips have 512 bytes NAND page size.
1010 #define NAND_ECC_STRENGTH(type)		((type)->ecc.strength_ds)
1011 #define NAND_ECC_STEP(type)		((type)->ecc.step_ds)
1014  * struct nand_flash_dev - NAND Flash Device ID Structure
1015  * @name: a human-readable name of the NAND chip
1022  * @pagesize: size of the NAND page in bytes; if 0, then the real page size (as
1023  *            well as the eraseblock size) is determined from the extended NAND
1030  * @ecc: ECC correctability and step information from the datasheet.
1031  * @ecc.strength_ds: The ECC correctability from the datasheet, same as the
1033  * @ecc.step_ds: The ECC step required by the @ecc.strength_ds, same as the
1035  *               For example, the "4bit ECC for each 512Byte" can be set with
1037  * @onfi_timing_mode_default: the default ONFI timing mode entered after a NAND
1060 	} ecc;  member
1065  * struct nand_manufacturers - NAND Flash Manufacturer ID Structure
1093  * struct platform_nand_chip - chip level device structure
1101  * @part_probe_types:	NULL-terminated array of probe types
1118  * struct platform_nand_ctrl - controller level device structure
1147  * struct platform_nand_data - container structure for platform-specific data
1160 	return chip->onfi_version ? le16_to_cpu(chip->onfi_params.features) : 0;  in onfi_feature()
1163 /* return the supported asynchronous timing mode. */
1166 	if (!chip->onfi_version)  in onfi_get_async_timing_mode()
1168 	return le16_to_cpu(chip->onfi_params.async_timing_mode);  in onfi_get_async_timing_mode()
1171 /* return the supported synchronous timing mode. */
1174 	if (!chip->onfi_version)  in onfi_get_sync_timing_mode()
1176 	return le16_to_cpu(chip->onfi_params.src_sync_timing_mode);  in onfi_get_sync_timing_mode()
1186  * Check if it is a SLC nand.
1187  * The !nand_is_slc() can be used to check the MLC/TLC nand chips.
1192 	return chip->bits_per_cell == 1;  in nand_is_slc()
1216 	return chip->jedec_version ? le16_to_cpu(chip->jedec_params.features)  in jedec_feature()
1220 /* Standard NAND functions from nand_base.c */
1227 /* get timing characteristics from ONFI timing mode. */
1228 const struct nand_sdr_timings *onfi_async_timing_mode_to_sdr_timings(int mode);
1229 /* get data interface from ONFI timing mode 0, used after reset. */
1233 				void *ecc, int ecclen,
1246 /* Reset and initialize a NAND device */
1249 /* NAND operation helpers */