Searched +full:max +full:- +full:memory +full:- +full:bandwidth (Results 1 – 25 of 515) sorted by relevance
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1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)4 ---5 $id: "http://devicetree.org/schemas/display/ti/ti,k2g-dss.yaml#"6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"11 - Jyri Sarha <jsarha@ti.com>12 - Tomi Valkeinen <tomi.valkeinen@ti.com>15 The K2G DSS is an ultra-light version of TI Keystone Display21 const: ti,k2g-dss25 - description: cfg DSS top level26 - description: common DISPC common[all …]
4 See Documentation/devicetree/bindings/display/ti/ti,omap-dss.txt for generic8 --------11 - compatible: "ti,omap2-dss"12 - reg: address and length of the register space13 - ti,hwmods: "dss_core"16 - Video port for DPI output19 - data-lines: number of lines used23 -----26 - compatible: "ti,omap2-dispc"27 - reg: address and length of the register space[all …]
4 See Documentation/devicetree/bindings/display/ti/ti,omap-dss.txt for generic8 --------11 - compatible: "ti,dra7-dss"12 - reg: address and length of the register spaces for 'dss'13 - ti,hwmods: "dss_core"14 - clocks: handle to fclk15 - clock-names: "fck"16 - syscon: phandle to control module core syscon node23 - reg: address and length of the register spaces for 'pll1_clkctrl',25 - clocks: handle to video1 pll clock and video2 pll clock[all …]
4 See Documentation/devicetree/bindings/display/ti/ti,omap-dss.txt for generic8 --------11 - compatible: "ti,omap3-dss"12 - reg: address and length of the register space13 - ti,hwmods: "dss_core"14 - clocks: handle to fclk15 - clock-names: "fck"18 - Video ports:19 - Port 0: DPI output20 - Port 1: SDI output[all …]
4 See Documentation/devicetree/bindings/display/ti/ti,omap-dss.txt for generic8 --------11 - compatible: "ti,omap5-dss"12 - reg: address and length of the register space13 - ti,hwmods: "dss_core"14 - clocks: handle to fclk15 - clock-names: "fck"18 - DISPC21 - DSS Submodules: RFBI, DSI, HDMI22 - Video port for DPI output[all …]
4 See Documentation/devicetree/bindings/display/ti/ti,omap-dss.txt for generic8 --------11 - compatible: "ti,omap4-dss"12 - reg: address and length of the register space13 - ti,hwmods: "dss_core"14 - clocks: handle to fclk15 - clock-names: "fck"18 - DISPC21 - DSS Submodules: RFBI, VENC, DSI, HDMI22 - Video port for DPI output[all …]
1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)4 ---5 $id: "http://devicetree.org/schemas/display/ti/ti,am65x-dss.yaml#"6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"11 - Jyri Sarha <jsarha@ti.com>12 - Tomi Valkeinen <tomi.valkeinen@ti.com>22 const: ti,am65x-dss26 Addresses to each DSS memory region described in the SoC's TRM.28 - description: common DSS register area29 - description: VIDL1 light video plane[all …]
1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)4 ---5 $id: "http://devicetree.org/schemas/display/ti/ti,j721e-dss.yaml#"6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"11 - Jyri Sarha <jsarha@ti.com>12 - Tomi Valkeinen <tomi.valkeinen@ti.com>22 const: ti,j721e-dss26 - description: common_m DSS Master common27 - description: common_s0 DSS Shared common 028 - description: common_s1 DSS Shared common 1[all …]
7 - compatible: must be one of:11 - reg: base address and size of the control registers block13 - interrupt-names: either the single entry "combined" representing a18 - interrupts: contains an interrupt specifier for each entry in19 interrupt-names21 - clock-names: should contain "clcdclk" and "apb_pclk"23 - clocks: contains phandle and clock specifier pairs for the entries24 in the clock-names property. See25 Documentation/devicetree/bindings/clock/clock-bindings.txt29 - memory-region: phandle to a node describing memory (see[all …]
8 share the same bandwidth. The bandwidth utilization can be partitioned18 - compatible: "qcom,hidma-mgmt-1.0";19 - reg: Address range for DMA device20 - dma-channels: Number of channels supported by this DMA controller.21 - max-write-burst-bytes: Maximum write burst in bytes that HIDMA can24 writing into destination memory. Setting this value incorrectly can26 - max-read-burst-bytes: Maximum read burst in bytes that HIDMA can29 reading the source memory. Setting this value incorrectly can starve31 - max-write-transactions: This value is how many times a write burst is34 - max-read-transactions: This value is how many times a read burst is[all …]
1 .. SPDX-License-Identifier: GPL-2.09 :Authors: - Fenghua Yu <fenghua.yu@intel.com>10 - Tony Luck <tony.luck@intel.com>11 - Vikas Shivappa <vikas.shivappa@intel.com>25 MBM (Memory Bandwidth Monitoring) "cqm_mbm_total", "cqm_mbm_local"26 MBA (Memory Bandwidth Allocation) "mba"31 # mount -t resctrl resctrl [-o cdp[,cdpl2][,mba_MBps]] /sys/fs/resctrl41 bandwidth in MBps47 pseudo-locking is a unique way of using cache control to "pin" or49 "Cache Pseudo-Locking".[all …]
1 // SPDX-License-Identifier: GPL-2.023 if (urb->transfer_flags & URB_FREE_BUFFER) in urb_destroy()24 kfree(urb->transfer_buffer); in urb_destroy()30 * usb_init_urb - initializes a urb so that it can be used by a USB driver38 * careful when freeing the memory for your urb that it is no longer in47 kref_init(&urb->kref); in usb_init_urb()48 INIT_LIST_HEAD(&urb->urb_list); in usb_init_urb()49 INIT_LIST_HEAD(&urb->anchor_list); in usb_init_urb()55 * usb_alloc_urb - creates a new urb for a USB driver to use57 * @mem_flags: the type of memory to allocate, see kmalloc() for a list of[all …]
1 * Rockchip DMC(Dynamic Memory Controller) device4 - compatible: Should be one of the following.5 - "rockchip,px30-dmc" - for PX30 SoCs.6 - "rockchip,rk1808-dmc" - for RK1808 SoCs.7 - "rockchip,rk3128-dmc" - for RK3128 SoCs.8 - "rockchip,rk3228-dmc" - for RK3228 SoCs.9 - "rockchip,rk3288-dmc" - for RK3288 SoCs.10 - "rockchip,rk3308-dmc" - for RK3308 SoCs.11 - "rockchip,rk3328-dmc" - for RK3328 SoCs.12 - "rockchip,rk3399-dmc" - for RK3399 SoCs.[all …]
5 - RK3566/RK35686 - RK3588/RK3588S7 - RV1103/RV11068 - RK356211 …rknn model must be generated using RKNN Toolkit 2: https://github.com/rockchip-linux/rknn-toolkit215 https://github.com/rockchip-linux/rknn-toolkit17 https://github.com/rockchip-linux/rknpu25 - Support RK356226 - Support more NPU operator fuse, such as Conv-Silu/Conv-Swish/Conv-Hardswish/Conv-sigmoid/Conv-Har…27 - Improve support for NHWC output layout[all …]
1 // SPDX-License-Identifier: MIT44 qi->dram_type = INTEL_DRAM_DDR4; in icl_pcode_read_mem_global_info()47 qi->dram_type = INTEL_DRAM_LPDDR4; in icl_pcode_read_mem_global_info()50 qi->dram_type = INTEL_DRAM_DDR3; in icl_pcode_read_mem_global_info()53 qi->dram_type = INTEL_DRAM_LPDDR3; in icl_pcode_read_mem_global_info()62 qi->dram_type = INTEL_DRAM_DDR4; in icl_pcode_read_mem_global_info()65 qi->dram_type = INTEL_DRAM_DDR3; in icl_pcode_read_mem_global_info()68 qi->dram_type = INTEL_DRAM_LPDDR3; in icl_pcode_read_mem_global_info()71 qi->dram_type = INTEL_DRAM_LPDDR4; in icl_pcode_read_mem_global_info()79 qi->dram_type = INTEL_DRAM_LPDDR3; /* Conservative default */ in icl_pcode_read_mem_global_info()[all …]
1 /* SPDX-License-Identifier: GPL-2.0 */49 #define MBM_CNTR_WIDTH_OFFSET_MAX (62 - MBM_CNTR_WIDTH_BASE)61 struct kernfs_fs_context *kfc = fc->fs_private; in rdt_fc2context()70 * struct mon_evt - Entry in the event list of a resource81 * struct mon_data_bits - Monitoring details for each event file116 * enum rdtgrp_mode - Mode of a RDT resource group119 * @RDT_MODE_PSEUDO_LOCKSETUP: Resource group will be used for Pseudo-Locking121 * allowed AND the allocations are Cache Pseudo-Locked128 * The "shareable", "exclusive", and "pseudo-locksetup" modes are set by130 * "pseudo-locked" mode after the schemata is written while the resource[all …]
1 // SPDX-License-Identifier: GPL-2.0-only4 * - Monitoring code46 * @rmid_entry - The entry in the limbo and free lists.63 * RMID available for re-allocation.72 WARN_ON(entry->rmid != rmid); in __rmid_entry()97 u64 val = __rmid_read(entry->rmid, QOS_L3_OCCUP_EVENT_ID); in rmid_dirty()123 nrmid = find_next_bit(d->rmid_busy_llc, r->num_rmid, crmid); in __check_limbo()124 if (nrmid >= r->num_rmid) in __check_limbo()129 clear_bit(entry->rmid, d->rmid_busy_llc); in __check_limbo()130 if (!--entry->busy) { in __check_limbo()[all …]
2 * SPDX-License-Identifier: MIT34 max_khz = policy->cpuinfo.max_freq; in cpu_max_MHz()50 struct drm_i915_private *i915 = llc_to_gt(llc)->i915; in get_ia_constants()51 struct intel_rps *rps = &llc_to_gt(llc)->rps; in get_ia_constants()56 if (rps->max_freq <= rps->min_freq) in get_ia_constants()59 consts->max_ia_freq = cpu_max_MHz(); in get_ia_constants()61 consts->min_ring_freq = in get_ia_constants()62 intel_uncore_read(llc_to_gt(llc)->uncore, DCLK) & 0xf; in get_ia_constants()63 /* convert DDR frequency from units of 266.6MHz to bandwidth */ in get_ia_constants()64 consts->min_ring_freq = mult_frac(consts->min_ring_freq, 8, 3); in get_ia_constants()[all …]
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23 * <<Broadcom-WL-IPTag/Dual:>>29 /* A chanspec holds the channel number, band, bandwidth and primary 20MHz sub-band */41 #define CH_160MHZ_APART (32u * CH_5MHZ_APART) /* 32 5Mhz-spaces */44 #define CH_MAX_2G_CHANNEL 14u /* Max channel in 2G band */46 #define CH_MAX_2G_40M_CHANNEL 11u /* Max 40MHz center channel in 2G band */49 #define CH_MAX_6G_CHANNEL 253u /* Max 20MHz channel in 6G band */51 #define CH_MAX_6G_40M_CHANNEL 227u /* Max 40MHz center channel in 6G band */53 #define CH_MAX_6G_80M_CHANNEL 215u /* Max 80MHz center channel in 6G band */55 #define CH_MAX_6G_160M_CHANNEL 207u /* Max 160MHz center channel in 6G band */57 #define CH_MAX_6G_240M_CHANNEL 167u /* Max 240MHz center channel in 6G band */[all …]
1 // SPDX-License-Identifier: GPL-2.07 * ice_sched_add_root_node - Insert the Tx scheduler root node in SW DB24 hw = pi->hw; in ice_sched_add_root_node()31 root->children = devm_kcalloc(ice_hw_to_dev(hw), hw->max_children[0], in ice_sched_add_root_node()33 if (!root->children) { in ice_sched_add_root_node()38 memcpy(&root->info, info, sizeof(*info)); in ice_sched_add_root_node()39 pi->root = root; in ice_sched_add_root_node()44 * ice_sched_find_node_by_teid - Find the Tx scheduler node in SW DB45 * @start_node: pointer to the starting ice_sched_node struct in a sub-tree50 * layers it has searched through; stopping at the max supported layer.[all …]
1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */7 * Copyright 1997--1999 Martin Mares <mj@ucw.cz>27 * Conventional PCI and PCI-X Mode 1 devices have 256 bytes of28 * configuration space. PCI-X Mode 2 and PCIe devices have 4096 bytes of43 #define PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */46 #define PCI_COMMAND_INVALIDATE 0x10 /* Use memory write and invalidate */51 #define PCI_COMMAND_FAST_BACK 0x200 /* Enable back-to-back writes */60 #define PCI_STATUS_FAST_BACK 0x80 /* Accept fast-back to back */90 * Base addresses specify locations in memory or I/O space.101 #define PCI_BASE_ADDRESS_SPACE 0x01 /* 0 = memory, 1 = I/O */[all …]
1 # SPDX-License-Identifier: GPL-2.0-only6 default "/lib/modules/$(shell,uname -r)/.config"7 default "/etc/kernel-config"8 default "/boot/config-$(shell,uname -r)"17 - Re-run Kconfig when the compiler is updated22 - Ensure full rebuild when the compier is updated24 fixdep adds include/config/cc/version/text.h into the auto-generated29 def_bool $(success,echo "$(CC_VERSION_TEXT)" | grep -q gcc)33 default $(shell,$(srctree)/scripts/gcc-version.sh $(CC)) if CC_IS_GCC38 default $(shell,$(LD) --version | $(srctree)/scripts/ld-version.sh)[all …]