1*4882a593SmuzhiyunTexas Instruments OMAP5 Display Subsystem 2*4882a593Smuzhiyun========================================= 3*4882a593Smuzhiyun 4*4882a593SmuzhiyunSee Documentation/devicetree/bindings/display/ti/ti,omap-dss.txt for generic 5*4882a593Smuzhiyundescription about OMAP Display Subsystem bindings. 6*4882a593Smuzhiyun 7*4882a593SmuzhiyunDSS Core 8*4882a593Smuzhiyun-------- 9*4882a593Smuzhiyun 10*4882a593SmuzhiyunRequired properties: 11*4882a593Smuzhiyun- compatible: "ti,omap5-dss" 12*4882a593Smuzhiyun- reg: address and length of the register space 13*4882a593Smuzhiyun- ti,hwmods: "dss_core" 14*4882a593Smuzhiyun- clocks: handle to fclk 15*4882a593Smuzhiyun- clock-names: "fck" 16*4882a593Smuzhiyun 17*4882a593SmuzhiyunRequired nodes: 18*4882a593Smuzhiyun- DISPC 19*4882a593Smuzhiyun 20*4882a593SmuzhiyunOptional nodes: 21*4882a593Smuzhiyun- DSS Submodules: RFBI, DSI, HDMI 22*4882a593Smuzhiyun- Video port for DPI output 23*4882a593Smuzhiyun 24*4882a593SmuzhiyunDPI Endpoint required properties: 25*4882a593Smuzhiyun- data-lines: number of lines used 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun 28*4882a593SmuzhiyunDISPC 29*4882a593Smuzhiyun----- 30*4882a593Smuzhiyun 31*4882a593SmuzhiyunRequired properties: 32*4882a593Smuzhiyun- compatible: "ti,omap5-dispc" 33*4882a593Smuzhiyun- reg: address and length of the register space 34*4882a593Smuzhiyun- ti,hwmods: "dss_dispc" 35*4882a593Smuzhiyun- interrupts: the DISPC interrupt 36*4882a593Smuzhiyun- clocks: handle to fclk 37*4882a593Smuzhiyun- clock-names: "fck" 38*4882a593Smuzhiyun 39*4882a593SmuzhiyunOptional properties: 40*4882a593Smuzhiyun- max-memory-bandwidth: Input memory (from main memory to dispc) bandwidth limit 41*4882a593Smuzhiyun in bytes per second 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun 44*4882a593SmuzhiyunRFBI 45*4882a593Smuzhiyun---- 46*4882a593Smuzhiyun 47*4882a593SmuzhiyunRequired properties: 48*4882a593Smuzhiyun- compatible: "ti,omap5-rfbi" 49*4882a593Smuzhiyun- reg: address and length of the register space 50*4882a593Smuzhiyun- ti,hwmods: "dss_rfbi" 51*4882a593Smuzhiyun- clocks: handles to fclk and iclk 52*4882a593Smuzhiyun- clock-names: "fck", "ick" 53*4882a593Smuzhiyun 54*4882a593SmuzhiyunOptional nodes: 55*4882a593Smuzhiyun- Video port for RFBI output 56*4882a593Smuzhiyun- RFBI controlled peripherals 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun 59*4882a593SmuzhiyunDSI 60*4882a593Smuzhiyun--- 61*4882a593Smuzhiyun 62*4882a593SmuzhiyunRequired properties: 63*4882a593Smuzhiyun- compatible: "ti,omap5-dsi" 64*4882a593Smuzhiyun- reg: addresses and lengths of the register spaces for 'proto', 'phy' and 'pll' 65*4882a593Smuzhiyun- reg-names: "proto", "phy", "pll" 66*4882a593Smuzhiyun- interrupts: the DSI interrupt line 67*4882a593Smuzhiyun- ti,hwmods: "dss_dsi1" or "dss_dsi2" 68*4882a593Smuzhiyun- vdd-supply: power supply for DSI 69*4882a593Smuzhiyun- clocks: handles to fclk and pll clock 70*4882a593Smuzhiyun- clock-names: "fck", "sys_clk" 71*4882a593Smuzhiyun 72*4882a593SmuzhiyunOptional nodes: 73*4882a593Smuzhiyun- Video port for DSI output 74*4882a593Smuzhiyun- DSI controlled peripherals 75*4882a593Smuzhiyun 76*4882a593SmuzhiyunDSI Endpoint required properties: 77*4882a593Smuzhiyun- lanes: list of pin numbers for the DSI lanes: CLK+, CLK-, DATA0+, DATA0-, 78*4882a593Smuzhiyun DATA1+, DATA1-, ... 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun 81*4882a593SmuzhiyunHDMI 82*4882a593Smuzhiyun---- 83*4882a593Smuzhiyun 84*4882a593SmuzhiyunRequired properties: 85*4882a593Smuzhiyun- compatible: "ti,omap5-hdmi" 86*4882a593Smuzhiyun- reg: addresses and lengths of the register spaces for 'wp', 'pll', 'phy', 87*4882a593Smuzhiyun 'core' 88*4882a593Smuzhiyun- reg-names: "wp", "pll", "phy", "core" 89*4882a593Smuzhiyun- interrupts: the HDMI interrupt line 90*4882a593Smuzhiyun- ti,hwmods: "dss_hdmi" 91*4882a593Smuzhiyun- vdda-supply: vdda power supply 92*4882a593Smuzhiyun- clocks: handles to fclk and pll clock 93*4882a593Smuzhiyun- clock-names: "fck", "sys_clk" 94*4882a593Smuzhiyun 95*4882a593SmuzhiyunOptional nodes: 96*4882a593Smuzhiyun- Video port for HDMI output 97*4882a593Smuzhiyun 98*4882a593SmuzhiyunHDMI Endpoint optional properties: 99*4882a593Smuzhiyun- lanes: list of 8 pin numbers for the HDMI lanes: CLK+, CLK-, D0+, D0-, 100*4882a593Smuzhiyun D1+, D1-, D2+, D2-. (default: 0,1,2,3,4,5,6,7) 101