1* Rockchip DMC(Dynamic Memory Controller) device 2 3Required properties: 4- compatible: Should be one of the following. 5 - "rockchip,px30-dmc" - for PX30 SoCs. 6 - "rockchip,rk1808-dmc" - for RK1808 SoCs. 7 - "rockchip,rk3128-dmc" - for RK3128 SoCs. 8 - "rockchip,rk3228-dmc" - for RK3228 SoCs. 9 - "rockchip,rk3288-dmc" - for RK3288 SoCs. 10 - "rockchip,rk3308-dmc" - for RK3308 SoCs. 11 - "rockchip,rk3328-dmc" - for RK3328 SoCs. 12 - "rockchip,rk3399-dmc" - for RK3399 SoCs. 13 - "rockchip,rk3528-dmc" - for RK3528 SoCs. 14 - "rockchip,rk3562-dmc" - for RK3562 SoCs. 15 - "rockchip,rk3568-dmc" - for RK3568 SoCs. 16 - "rockchip,rk3588-dmc" - for RK3588 SoCs. 17 - "rockchip,rv1126-dmc" - for RV1126 SoCs. 18- devfreq-events: Node to get DDR loading, Refer to 19 Documentation/devicetree/bindings/devfreq/rockchip-dfi.txt 20- interrupts: The interrupt number to the CPU. The interrupt specifier format 21 depends on the interrupt controller. It should be DCF interrupts, 22 when DDR dvfs finish, it will happen. 23- clocks: Phandles for clock specified in "clock-names" property 24- clock-names : The name of clock used by the DFI, must be "pclk_ddr_mon"; 25- operating-points-v2: Refer to Documentation/devicetree/bindings/power/opp.txt 26 for details. 27- center-supply: DMC supply node. 28- status: Marks the node enabled/disabled. 29 30Optional properties: 31- ddr_timing: DDR timing need to pass to arm trust firmware 32- upthreshold: The upthreshold to simpleondeamnd policy 33- downdifferential: The downdifferential to simpleondeamnd policy 34- vop-bw-dmc-freq: The property is an array of 3-tuples items, and 35 each item consists of bandwidth and frequency like 36 <min-bandwidth max-bandwidth frequency>. 37 min-bandwidth: minimum ddr bandwidth in Mbyte/sec. 38 max-bandwidth: maximum ddr bandwidth in Mbyte/sec. 39 frequency: ddr frequency in KHz. 40- #cooling-cells: This property indicates dmc can work as a cooling device 41- ddr_power_model: Sets power model parameters. 42 - dynamic-power-coefficient: A u32 value that represents the running time dynamic 43 power coefficient in units of mW/MHz/uVolt^2. The coefficient can either be 44 calculated from power measurements or derived by analysis. 45 - static-power-coefficient: A u32 value that represents the static power 46 coefficient. 47 - ts: An array containing coefficients for the temperature scaling factor. 48 Used as : tsf = ts[3]*T^3 + ts[2]*T^2 + ts[1]*T + ts[0], where T = temperature 49 - thermal-zone: A string identifying the thermal zone used for the dmc 50 51Example: 52 53 ddr_timing: ddr_timing { 54 compatible = "rockchip,ddr-timing"; 55 ddr3_speed_bin = <21>; 56 pd_idle = <0>; 57 sr_idle = <0>; 58 sr_mc_gate_idle = <0>; 59 srpd_lite_idle = <0>; 60 standby_idle = <0>; 61 dram_dll_dis_freq = <300>; 62 phy_dll_dis_freq = <125>; 63 64 ddr3_odt_dis_freq = <333>; 65 ddr3_drv = <DDR3_DS_40ohm>; 66 ddr3_odt = <DDR3_ODT_120ohm>; 67 phy_ddr3_ca_drv = <PHY_DRV_ODT_40>; 68 phy_ddr3_dq_drv = <PHY_DRV_ODT_40>; 69 phy_ddr3_odt = <PHY_DRV_ODT_240>; 70 71 lpddr3_odt_dis_freq = <333>; 72 lpddr3_drv = <LP3_DS_34ohm>; 73 lpddr3_odt = <LP3_ODT_240ohm>; 74 phy_lpddr3_ca_drv = <PHY_DRV_ODT_40>; 75 phy_lpddr3_dq_drv = <PHY_DRV_ODT_40>; 76 phy_lpddr3_odt = <PHY_DRV_ODT_240>; 77 78 lpddr4_odt_dis_freq = <333>; 79 lpddr4_drv = <LP4_PDDS_60ohm>; 80 lpddr4_dq_odt = <LP4_DQ_ODT_40ohm>; 81 lpddr4_ca_odt = <LP4_CA_ODT_40ohm>; 82 phy_lpddr4_ca_drv = <PHY_DRV_ODT_40>; 83 phy_lpddr4_ck_cs_drv = <PHY_DRV_ODT_80>; 84 phy_lpddr4_dq_drv = <PHY_DRV_ODT_80>; 85 phy_lpddr4_odt = <PHY_DRV_ODT_60>; 86 }; 87 88 dmc_opp_table: dmc_opp_table { 89 compatible = "operating-points-v2"; 90 91 opp00 { 92 opp-hz = /bits/ 64 <300000000>; 93 opp-microvolt = <900000>; 94 }; 95 opp01 { 96 opp-hz = /bits/ 64 <666000000>; 97 opp-microvolt = <900000>; 98 }; 99 }; 100 101 dmc: dmc { 102 compatible = "rockchip,rk3399-dmc"; 103 devfreq-events = <&dfi>; 104 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 105 clocks = <&cru SCLK_DDRCLK>; 106 clock-names = "dmc_clk"; 107 ddr_timing = <&ddr_timing>; 108 operating-points-v2 = <&dmc_opp_table>; 109 center-supply = <&ppvar_centerlogic>; 110 upthreshold = <15>; 111 downdifferential = <10>; 112 #cooling-cells = <2>; 113 ddr_power_model: ddr_power_model { 114 dynamic-power-coefficient = <120>; 115 static-power-coefficient = <300>; 116 ts = <32000 4700 (-80) 2>; 117 thermal-zone = "soc-thermal"; 118 } 119 status = "disabled"; 120 }; 121