xref: /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/display/arm,pl11x.txt (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun* ARM PrimeCell Color LCD Controller PL110/PL111
2*4882a593Smuzhiyun
3*4882a593SmuzhiyunSee also Documentation/devicetree/bindings/arm/primecell.yaml
4*4882a593Smuzhiyun
5*4882a593SmuzhiyunRequired properties:
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun- compatible: must be one of:
8*4882a593Smuzhiyun	"arm,pl110", "arm,primecell"
9*4882a593Smuzhiyun	"arm,pl111", "arm,primecell"
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun- reg: base address and size of the control registers block
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun- interrupt-names: either the single entry "combined" representing a
14*4882a593Smuzhiyun	combined interrupt output (CLCDINTR), or the four entries
15*4882a593Smuzhiyun	"mbe", "vcomp", "lnbu", "fuf" representing the individual
16*4882a593Smuzhiyun	CLCDMBEINTR, CLCDVCOMPINTR, CLCDLNBUINTR, CLCDFUFINTR interrupts
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun- interrupts: contains an interrupt specifier for each entry in
19*4882a593Smuzhiyun	interrupt-names
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun- clock-names: should contain "clcdclk" and "apb_pclk"
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun- clocks: contains phandle and clock specifier pairs for the entries
24*4882a593Smuzhiyun	in the clock-names property. See
25*4882a593Smuzhiyun	Documentation/devicetree/bindings/clock/clock-bindings.txt
26*4882a593Smuzhiyun
27*4882a593SmuzhiyunOptional properties:
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun- memory-region: phandle to a node describing memory (see
30*4882a593Smuzhiyun	Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt)
31*4882a593Smuzhiyun	to be used for the framebuffer; if not present, the framebuffer
32*4882a593Smuzhiyun	may be located anywhere in the memory
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun- max-memory-bandwidth: maximum bandwidth in bytes per second that the
35*4882a593Smuzhiyun	cell's memory interface can handle; if not present, the memory
36*4882a593Smuzhiyun	interface is fast enough to handle all possible video modes
37*4882a593Smuzhiyun
38*4882a593SmuzhiyunRequired sub-nodes:
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun- port: describes LCD panel signals, following the common binding
41*4882a593Smuzhiyun	for video transmitter interfaces; see
42*4882a593Smuzhiyun	Documentation/devicetree/bindings/media/video-interfaces.txt
43*4882a593Smuzhiyun
44*4882a593SmuzhiyunDeprecated properties:
45*4882a593Smuzhiyun	The port's endbpoint subnode had this, now deprecated property
46*4882a593Smuzhiyun	in the past. Drivers should be able to survive without it:
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun	- arm,pl11x,tft-r0g0b0-pads: an array of three 32-bit values,
49*4882a593Smuzhiyun		defining the way CLD pads are wired up; first value
50*4882a593Smuzhiyun		contains index of the "CLD" external pin (pad) used
51*4882a593Smuzhiyun		as R0 (first bit of the red component), second value
52*4882a593Smuzhiyun	        index of the pad used as G0, third value index of the
53*4882a593Smuzhiyun		pad used as B0, see also "LCD panel signal multiplexing
54*4882a593Smuzhiyun		details" paragraphs in the PL110/PL111 Technical
55*4882a593Smuzhiyun		Reference Manuals; this implicitly defines available
56*4882a593Smuzhiyun		color modes, for example:
57*4882a593Smuzhiyun		- PL111 TFT 4:4:4 panel:
58*4882a593Smuzhiyun			arm,pl11x,tft-r0g0b0-pads = <4 15 20>;
59*4882a593Smuzhiyun		- PL110 TFT (1:)5:5:5 panel:
60*4882a593Smuzhiyun			arm,pl11x,tft-r0g0b0-pads = <1 7 13>;
61*4882a593Smuzhiyun		- PL111 TFT (1:)5:5:5 panel:
62*4882a593Smuzhiyun			arm,pl11x,tft-r0g0b0-pads = <3 11 19>;
63*4882a593Smuzhiyun		- PL111 TFT 5:6:5 panel:
64*4882a593Smuzhiyun			arm,pl11x,tft-r0g0b0-pads = <3 10 19>;
65*4882a593Smuzhiyun		- PL110 and PL111 TFT 8:8:8 panel:
66*4882a593Smuzhiyun			arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
67*4882a593Smuzhiyun		- PL110 and PL111 TFT 8:8:8 panel, R & B components swapped:
68*4882a593Smuzhiyun			arm,pl11x,tft-r0g0b0-pads = <16 8 0>;
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun
71*4882a593SmuzhiyunExample:
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun	clcd@10020000 {
74*4882a593Smuzhiyun		compatible = "arm,pl111", "arm,primecell";
75*4882a593Smuzhiyun		reg = <0x10020000 0x1000>;
76*4882a593Smuzhiyun		interrupt-names = "combined";
77*4882a593Smuzhiyun		interrupts = <0 44 4>;
78*4882a593Smuzhiyun		clocks = <&oscclk1>, <&oscclk2>;
79*4882a593Smuzhiyun		clock-names = "clcdclk", "apb_pclk";
80*4882a593Smuzhiyun		max-memory-bandwidth = <94371840>; /* Bps, 1024x768@60 16bpp */
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun		port {
83*4882a593Smuzhiyun			clcd_pads: endpoint {
84*4882a593Smuzhiyun				remote-endpoint = <&clcd_panel>;
85*4882a593Smuzhiyun			};
86*4882a593Smuzhiyun		};
87*4882a593Smuzhiyun
88*4882a593Smuzhiyun	};
89*4882a593Smuzhiyun
90*4882a593Smuzhiyun	panel {
91*4882a593Smuzhiyun		compatible = "panel-dpi";
92*4882a593Smuzhiyun
93*4882a593Smuzhiyun		port {
94*4882a593Smuzhiyun			clcd_panel: endpoint {
95*4882a593Smuzhiyun				remote-endpoint = <&clcd_pads>;
96*4882a593Smuzhiyun			};
97*4882a593Smuzhiyun		};
98*4882a593Smuzhiyun
99*4882a593Smuzhiyun		panel-timing {
100*4882a593Smuzhiyun			clock-frequency = <25175000>;
101*4882a593Smuzhiyun			hactive = <640>;
102*4882a593Smuzhiyun			hback-porch = <40>;
103*4882a593Smuzhiyun			hfront-porch = <24>;
104*4882a593Smuzhiyun			hsync-len = <96>;
105*4882a593Smuzhiyun			vactive = <480>;
106*4882a593Smuzhiyun			vback-porch = <32>;
107*4882a593Smuzhiyun			vfront-porch = <11>;
108*4882a593Smuzhiyun			vsync-len = <2>;
109*4882a593Smuzhiyun		};
110*4882a593Smuzhiyun	};
111