1*4882a593SmuzhiyunTexas Instruments DRA7x Display Subsystem 2*4882a593Smuzhiyun========================================= 3*4882a593Smuzhiyun 4*4882a593SmuzhiyunSee Documentation/devicetree/bindings/display/ti/ti,omap-dss.txt for generic 5*4882a593Smuzhiyundescription about OMAP Display Subsystem bindings. 6*4882a593Smuzhiyun 7*4882a593SmuzhiyunDSS Core 8*4882a593Smuzhiyun-------- 9*4882a593Smuzhiyun 10*4882a593SmuzhiyunRequired properties: 11*4882a593Smuzhiyun- compatible: "ti,dra7-dss" 12*4882a593Smuzhiyun- reg: address and length of the register spaces for 'dss' 13*4882a593Smuzhiyun- ti,hwmods: "dss_core" 14*4882a593Smuzhiyun- clocks: handle to fclk 15*4882a593Smuzhiyun- clock-names: "fck" 16*4882a593Smuzhiyun- syscon: phandle to control module core syscon node 17*4882a593Smuzhiyun 18*4882a593SmuzhiyunOptional properties: 19*4882a593Smuzhiyun 20*4882a593SmuzhiyunSome DRA7xx SoCs have one dedicated video PLL, some have two. These properties 21*4882a593Smuzhiyuncan be used to describe the video PLLs: 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun- reg: address and length of the register spaces for 'pll1_clkctrl', 24*4882a593Smuzhiyun 'pll1', 'pll2_clkctrl', 'pll2' 25*4882a593Smuzhiyun- clocks: handle to video1 pll clock and video2 pll clock 26*4882a593Smuzhiyun- clock-names: "video1_clk" and "video2_clk" 27*4882a593Smuzhiyun 28*4882a593SmuzhiyunRequired nodes: 29*4882a593Smuzhiyun- DISPC 30*4882a593Smuzhiyun 31*4882a593SmuzhiyunOptional nodes: 32*4882a593Smuzhiyun- DSS Submodules: HDMI 33*4882a593Smuzhiyun- Video port for DPI output 34*4882a593Smuzhiyun 35*4882a593SmuzhiyunDPI Endpoint required properties: 36*4882a593Smuzhiyun- data-lines: number of lines used 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun 39*4882a593SmuzhiyunDISPC 40*4882a593Smuzhiyun----- 41*4882a593Smuzhiyun 42*4882a593SmuzhiyunRequired properties: 43*4882a593Smuzhiyun- compatible: "ti,dra7-dispc" 44*4882a593Smuzhiyun- reg: address and length of the register space 45*4882a593Smuzhiyun- ti,hwmods: "dss_dispc" 46*4882a593Smuzhiyun- interrupts: the DISPC interrupt 47*4882a593Smuzhiyun- clocks: handle to fclk 48*4882a593Smuzhiyun- clock-names: "fck" 49*4882a593Smuzhiyun 50*4882a593SmuzhiyunOptional properties: 51*4882a593Smuzhiyun- max-memory-bandwidth: Input memory (from main memory to dispc) bandwidth limit 52*4882a593Smuzhiyun in bytes per second 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun 55*4882a593SmuzhiyunHDMI 56*4882a593Smuzhiyun---- 57*4882a593Smuzhiyun 58*4882a593SmuzhiyunRequired properties: 59*4882a593Smuzhiyun- compatible: "ti,dra7-hdmi" 60*4882a593Smuzhiyun- reg: addresses and lengths of the register spaces for 'wp', 'pll', 'phy', 61*4882a593Smuzhiyun 'core' 62*4882a593Smuzhiyun- reg-names: "wp", "pll", "phy", "core" 63*4882a593Smuzhiyun- interrupts: the HDMI interrupt line 64*4882a593Smuzhiyun- ti,hwmods: "dss_hdmi" 65*4882a593Smuzhiyun- vdda-supply: vdda power supply 66*4882a593Smuzhiyun- clocks: handles to fclk and pll clock 67*4882a593Smuzhiyun- clock-names: "fck", "sys_clk" 68*4882a593Smuzhiyun 69*4882a593SmuzhiyunOptional nodes: 70*4882a593Smuzhiyun- Video port for HDMI output 71*4882a593Smuzhiyun 72*4882a593SmuzhiyunHDMI Endpoint optional properties: 73*4882a593Smuzhiyun- lanes: list of 8 pin numbers for the HDMI lanes: CLK+, CLK-, D0+, D0-, 74*4882a593Smuzhiyun D1+, D1-, D2+, D2-. (default: 0,1,2,3,4,5,6,7) 75