| /OK3568_Linux_fs/u-boot/board/freescale/t208xqds/ |
| H A D | README | 1 The T2080QDS is a high-performance computing evaluation, development and
5 ------------------
6 The T2080 QorIQ multicore processor combines four dual-threaded e6500 Power
7 Architecture processor cores with high-performance datapath acceleration
12 - Four dual-threads 64-bit Power architecture e6500 cores, up to 1.8GHz
13 - 2MB L2 cache and 512KB CoreNet platform cache (CPC)
14 - Hierarchical interconnect fabric
15 - One 32-/64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving
16 - Data Path Acceleration Architecture (DPAA) incorporating acceleration
17 - 16 SerDes lanes up to 10.3125 GHz
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| /OK3568_Linux_fs/u-boot/board/freescale/t208xrdb/ |
| H A D | README | 1 T2080PCIe-RDB is a Freescale Reference Design Board that hosts the T2080 SoC.
5 ------------------
6 The T2080 QorIQ multicore processor combines four dual-threaded e6500 Power
7 Architecture processor cores with high-performance datapath acceleration
12 - Four dual-threads 64-bit Power architecture e6500 cores, up to 1.8GHz
13 - 2MB L2 cache and 512KB CoreNet platform cache (CPC)
14 - Hierarchical interconnect fabric
15 - One 32-/64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving
16 - Data Path Acceleration Architecture (DPAA) incorporating acceleration
17 - 16 SerDes lanes up to 10.3125 GHz
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| /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/media/i2c/ |
| H A D | imx219.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Sony 1/4.0-Inch 8Mpixel CMOS Digital Image Sensor
10 - Dave Stevenson <dave.stevenson@raspberrypi.com>
12 description: |-
13 The Sony imx219 is a 1/4.0-inch CMOS active pixel digital image sensor
16 Image data is sent through MIPI CSI-2, which is configured as either 2 or
30 VDIG-supply:
34 VANA-supply:
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| H A D | tc358743.txt | 1 * Toshiba TC358743 HDMI-RX to MIPI CSI2-TX Bridge
3 The Toshiba TC358743 HDMI-RX to MIPI CSI2-TX (H2C) is a bridge that converts
4 a HDMI stream to MIPI CSI-2 TX. It is programmable through I2C.
8 - compatible: value should be "toshiba,tc358743"
9 - clocks, clock-names: should contain a phandle link to the reference clock
14 - reset-gpios: gpio phandle GPIO connected to the reset pin
15 - interrupts: GPIO connected to the interrupt pin
16 - data-lanes: should be <1 2 3 4> for four-lane operation,
17 or <1 2> for two-lane operation
18 - clock-lanes: should be <0>
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| H A D | rk628.txt | 1 * RK628 HDMI-RX to MIPI CSI2-TX Bridge
3 The RK628 HDMI-RX to MIPI CSI2-TX (H2C) is a bridge that converts
4 a HDMI stream to MIPI CSI-2 TX. It is programmable through I2C.
7 - compatible: value should be "rockchip,rk628-csi-v4l2"
8 - reg: I2C device address
11 - reset-gpios: gpio phandle GPIO connected to the reset pin
12 - enable-gpios: a GPIO spec for the enable pin
13 - plugin-det-gpios: HDMI 5V detect pin
14 - interrupts: GPIO connected to the interrupt pin
15 - data-lanes: should be <1 2 3 4> for four-lane operation,
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| H A D | lt7911d.txt | 1 * Lontium lt7911d type-c/DP to MIPI-CSI Bridge
4 - compatible: should be "lontium,lt7911d".
5 - clocks: reference to the 27M xvclk input clock.
6 - clock-names: should be "xvclk".
7 - reset-gpios: Low active reset gpio.
8 - power-gpios: High active power gpio.
9 - hpd-ctl-gpios: High active hpd control gpio.
11 - plugin-det-gpios: Low active plugin detect gpio.
12 - interrupts: GPIO connected to the gpio5.
13 - data-lanes: should be <1 2 3 4> for four-lane operation,
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| H A D | ov8856.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Dongchun Zhu <dongchun.zhu@mediatek.com>
13 description: |-
14 The Omnivision OV8856 is a high performance, 1/4-inch, 8 megapixel, CMOS
15 image sensor that delivers 3264x2448 at 30fps. It provides full-frame,
16 sub-sampled, and windowed 10-bit MIPI images in various formats via the
18 through I2C and two-wire SCCB. The sensor output is available via CSI-2
19 serial data output (up to 4-lane).
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| H A D | lt7911uxc.txt | 1 * Lontium lt7911uxc type-c/DP to MIPI-CSI Bridge
4 - compatible: should be "lontium,lt7911uxc".
5 - clocks: reference to the 27M xvclk input clock.
6 - clock-names: should be "xvclk".
7 - reset-gpios: Low active reset gpio.
8 - power-gpios: High active power gpio.
9 - plugin-det-gpios: Low active plugin detect gpio.
10 - interrupts: GPIO connected to lt7911uxc gpio0.
11 - data-lanes: should be <1 2 3 4> for four-lane DPHY,
12 or <1 2 3> for three-trios CPHY.
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| /OK3568_Linux_fs/u-boot/arch/arm/cpu/armv8/fsl-layerscape/doc/ |
| H A D | README.soc | 11 ---------
12 The LS1043A integrated multicore processor combines four ARM Cortex-A53
18 - Four 64-bit ARM Cortex-A53 CPUs
19 - 1 MB unified L2 Cache
20 - One 32-bit DDR3L/DDR4 SDRAM memory controllers with ECC and interleaving
22 - Data Path Acceleration Architecture (DPAA) incorporating acceleration the
24 - Packet parsing, classification, and distribution (FMan)
25 - Queue management for scheduling, packet sequencing, and congestion
27 - Hardware buffer management for buffer allocation and de-allocation (BMan)
28 - Cryptography acceleration (SEC)
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| /OK3568_Linux_fs/u-boot/board/freescale/p2041rdb/ |
| H A D | README | 3 The P2041 Processor combines four Power Architecture processor cores
4 with high-performance datapath acceleration architecture(DPAA), CoreNet
19 => tftp 1000000 u-boot.bin
36 5. Change DIP-switch
37 SW1[1-5] = 10110
48 SDCard which contains RCW and U-Boot image.
59 5. Change DIP-switch
60 SW1[1-5] = 01100
71 SPI flash which contains RCW and U-Boot image.
84 5. Change DIP-switch
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| H A D | eth.c | 5 * SPDX-License-Identifier: GPL-2.0+
9 * The RGMII PHYs are provided by the two on-board PHY. The SGMII PHYs
10 * are provided by the three on-board PHY or by the standard Freescale
11 * four-port SGMII riser card. We need to change the phy-handle in the
30 * that the mapping must be determined dynamically, or that the lane maps to
67 * ... update the phy-handle property of the Ethernet node to point to the
75 * ports in U-Boot because on previous Ethernet devices (e.g. Gianfar), MACs
93 int lane = serdes_get_first_lane(SGMII_FM1_DTSEC1 + port); in board_ft_fman_fixup_port() local
95 if (lane < 0) in board_ft_fman_fixup_port()
97 slot = lane_to_slot[lane]; in board_ft_fman_fixup_port()
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| /OK3568_Linux_fs/kernel/arch/mips/cavium-octeon/executive/ |
| H A D | cvmx-helper-errata.c | 7 * Copyright (c) 2003-2008 Cavium Networks
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
31 * contains functions called by cvmx-helper to workaround known
40 #include <asm/octeon/cvmx-helper-jtag.h>
43 * Due to errata G-720, the 2nd order CDR circuit on CN52XX pass
51 int lane; in __cvmx_helper_errata_qlm_disable_2nd_order_cdr() local
53 /* We need to load all four lanes of the QLM, a total of 1072 bits */ in __cvmx_helper_errata_qlm_disable_2nd_order_cdr()
54 for (lane = 0; lane < 4; lane++) { in __cvmx_helper_errata_qlm_disable_2nd_order_cdr()
56 * Each lane has 268 bits. We need to set in __cvmx_helper_errata_qlm_disable_2nd_order_cdr()
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| /OK3568_Linux_fs/u-boot/board/freescale/ls2080aqds/ |
| H A D | README | 2 --------
3 The LS2080A Development System (QDS) is a high-performance computing,
10 --------------------
11 Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS2080A,
15 -----------------------
16 - SERDES Connections, 16 lanes supporting:
17 - PCI Express - 3.0
18 - SGMII, SGMII 2.5
19 - QSGMII
20 - SATA 3.0
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| /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/display/bridge/ |
| H A D | ps8640.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Nicolas Boichat <drinkcat@chromium.org>
11 - Enric Balletbo i Serra <enric.balletbo@collabora.com>
14 The PS8640 is a low power MIPI-to-eDP video format converter supporting
16 device accepts a single channel of MIPI DSI v1.1, with up to four lanes
17 plus clock, at a transmission rate up to 1.5Gbit/sec per lane. The
19 3.24Gbit/sec per lane.
29 powerdown-gpios:
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| /OK3568_Linux_fs/u-boot/board/freescale/ls1021atwr/ |
| H A D | README | 2 --------
6 ------------------
8 is built on Layerscape architecture, the industry's first software-aware,
9 core-agnostic networking architecture to offer unprecedented efficiency
12 A member of the value-performance tier, the QorIQ LS1021A processor provides
14 enterprise networking applications. Incorporating dual ARM Cortex-A7 cores
15 running up to 1.0 GHz, the LS1021A processor delivers pre-silicon CoreMark
17 security features and the broadest array of high-speed interconnects and
18 optimized peripheral features ever offered in a sub-3 W processor.
23 protection on both L1 and L2 caches. The LS1021A processor is pin- and
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| /OK3568_Linux_fs/u-boot/board/freescale/ls1021aqds/ |
| H A D | README | 2 --------
6 ------------------
8 is built on Layerscape architecture, the industry's first software-aware,
9 core-agnostic networking architecture to offer unprecedented efficiency
12 A member of the value-performance tier, the QorIQ LS1021A processor provides
14 enterprise networking applications. Incorporating dual ARM Cortex-A7 cores
15 running up to 1.0 GHz, the LS1021A processor delivers pre-silicon CoreMark
17 security features and the broadest array of high-speed interconnects and
18 optimized peripheral features ever offered in a sub-3 W processor.
23 protection on both L1 and L2 caches. The LS1021A processor is pin- and
[all …]
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| /OK3568_Linux_fs/u-boot/board/freescale/t1040qds/ |
| H A D | eth.c | 4 * SPDX-License-Identifier: GPL-2.0+
8 * The RGMII PHYs are provided by the two on-board PHY connected to
9 * dTSEC instances 4 and 5. The SGMII PHYs are provided by one on-board
10 * PHY or by the standard four-port SGMII riser card (VSC).
29 /* - In T1040 there are only 8 SERDES lanes, spread across 2 SERDES banks.
30 * Bank 1 -> Lanes A, B, C, D
31 * Bank 2 -> Lanes E, F, G, H
35 * means that the mapping must be determined dynamically, or that the lane
121 struct t1040_qds_mdio *priv = bus->priv; in t1040_qds_mdio_read()
123 t1040_qds_mux_mdio(priv->muxval); in t1040_qds_mdio_read()
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| /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/phy/ |
| H A D | ti,phy-j721e-wiz.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
4 ---
5 $id: "http://devicetree.org/schemas/phy/ti,phy-j721e-wiz.yaml#"
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
11 - Kishon Vijay Abraham I <kishon@ti.com>
16 - ti,j721e-wiz-16g
17 - ti,j721e-wiz-10g
19 power-domains:
24 description: clock-specifier to represent input to the WIZ
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| /OK3568_Linux_fs/u-boot/board/freescale/bsc9132qds/ |
| H A D | README | 2 --------
4 Microcell, Picocell, and Enterprise-Femto base station market subsegments.
7 core technologies with MAPLE-B2P baseband acceleration processing elements
15 - Power Architecture subsystem including two e500 processors with
16 512-Kbyte shared L2 cache
17 - Two StarCore SC3850 DSP subsystems, each with a 512-Kbyte private L2
19 - 32 Kbyte of shared M3 memory
20 - The Multi Accelerator Platform Engine for Pico BaseStation Baseband
21 Processing (MAPLE-B2P)
22 - Two DDR3/3L memory interfaces with 32-bit data width (40 bits including
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| /OK3568_Linux_fs/kernel/drivers/nvdimm/ |
| H A D | btt.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
4 * Copyright (c) 2014-2015, Intel Corporation.
49 * A log group represents one log 'lane', and consists of four log entries.
50 * Two of the four entries are valid entries, and the remaining two are
60 * +-----------------+-----------------+
64 * +-----------------------------------+
68 * +-----------------+-----------------+
71 * +-----------------+-----------------+
75 * +-----------------------------------+
79 * +-----------------+-----------------+
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| /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/pci/ |
| H A D | mvebu-pci.txt | 5 - compatible: one of the following values:
6 marvell,armada-370-pcie
7 marvell,armada-xp-pcie
8 marvell,dove-pcie
9 marvell,kirkwood-pcie
10 - #address-cells, set to <3>
11 - #size-cells, set to <2>
12 - #interrupt-cells, set to <1>
13 - bus-range: PCI bus numbers covered
14 - device_type, set to "pci"
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| H A D | ti-pci.txt | 4 - compatible: Should be "ti,dra7-pcie" for RC (deprecated)
5 Should be "ti,dra7-pcie-ep" for EP (deprecated)
6 Should be "ti,dra746-pcie-rc" for dra74x/dra76 in RC mode
7 Should be "ti,dra746-pcie-ep" for dra74x/dra76 in EP mode
8 Should be "ti,dra726-pcie-rc" for dra72x in RC mode
9 Should be "ti,dra726-pcie-ep" for dra72x in EP mode
10 - phys : list of PHY specifiers (used by generic PHY framework)
11 - phy-names : must be "pcie-phy0", "pcie-phy1", "pcie-phyN".. based on the
13 - ti,hwmods : Name of the hwmod associated to the pcie, "pcie<X>",
15 - num-lanes as specified in ../designware-pcie.txt
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| /OK3568_Linux_fs/u-boot/board/freescale/corenet_ds/ |
| H A D | eth_hydra.c | 2 * Copyright 2009-2011 Freescale Semiconductor, Inc.
5 * SPDX-License-Identifier: GPL-2.0+
11 * board. The RGMII PHYs are the two on-board 1Gb ports. The SGMII PHYs are
12 * provided by the standard Freescale four-port SGMII riser card. The 10Gb
34 * 2) The phy-handle property of each active Ethernet MAC node is set to the
39 * values, so those values are hard-coded in the DTS. On the HYDRA board,
47 * and might need to be enabled, and also might need to have its mux-value
94 * that the mapping must be determined dynamically, or that the lane maps to
108 clrsetbits_8(&pixis->brdcfg1, mask, val); in hydra_mux_mdio()
120 struct hydra_mdio *priv = bus->priv; in hydra_mdio_read()
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| H A D | eth_superhydra.c | 2 * Copyright 2009-2011 Freescale Semiconductor, Inc.
5 * SPDX-License-Identifier: GPL-2.0+
11 * board. The RGMII PHYs are the two on-board 1Gb ports. The SGMII PHYs are
12 * provided by the standard Freescale four-port SGMII riser card. The 10Gb
34 * 2) The phy-handle property of each active Ethernet MAC node is set to the
39 * values, so those values are hard-coded in the DTS. On the HYDRA board,
47 * and might need to be enabled, and also might need to have its mux-value
99 * that the mapping must be determined dynamically, or that the lane maps to
113 clrsetbits_8(&pixis->brdcfg1, mask, val); in super_hydra_mux_mdio()
125 struct super_hydra_mdio *priv = bus->priv; in super_hydra_mdio_read()
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| /OK3568_Linux_fs/kernel/drivers/gpu/drm/bridge/ |
| H A D | tc358764.c | 1 // SPDX-License-Identifier: GPL-2.0
28 #define FLD_MASK(start, end) (((1 << ((start) - (end) + 1)) - 1) << (end))
34 #define PPI_LANEENABLE 0x0134 /* Enables each lane */
36 #define PPI_D0S_CLRSIPOCOUNT 0x0164 /* Assertion timer for Lane 0 */
37 #define PPI_D1S_CLRSIPOCOUNT 0x0168 /* Assertion timer for Lane 1 */
38 #define PPI_D2S_CLRSIPOCOUNT 0x016C /* Assertion timer for Lane 2 */
39 #define PPI_D3S_CLRSIPOCOUNT 0x0170 /* Assertion timer for Lane 3 */
43 #define DSI_STARTDSI 0x0204 /* START control bit of DSI-TX */
44 #define DSI_LANEENABLE 0x0210 /* Enables each lane */
125 #define SYS_RST_I2CS BIT(0) /* Reset I2C-Slave controller */
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