1*4882a593Smuzhiyun /***********************license start***************
2*4882a593Smuzhiyun * Author: Cavium Networks
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * Contact: support@caviumnetworks.com
5*4882a593Smuzhiyun * This file is part of the OCTEON SDK
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * Copyright (c) 2003-2008 Cavium Networks
8*4882a593Smuzhiyun *
9*4882a593Smuzhiyun * This file is free software; you can redistribute it and/or modify
10*4882a593Smuzhiyun * it under the terms of the GNU General Public License, Version 2, as
11*4882a593Smuzhiyun * published by the Free Software Foundation.
12*4882a593Smuzhiyun *
13*4882a593Smuzhiyun * This file is distributed in the hope that it will be useful, but
14*4882a593Smuzhiyun * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15*4882a593Smuzhiyun * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16*4882a593Smuzhiyun * NONINFRINGEMENT. See the GNU General Public License for more
17*4882a593Smuzhiyun * details.
18*4882a593Smuzhiyun *
19*4882a593Smuzhiyun * You should have received a copy of the GNU General Public License
20*4882a593Smuzhiyun * along with this file; if not, write to the Free Software
21*4882a593Smuzhiyun * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22*4882a593Smuzhiyun * or visit http://www.gnu.org/licenses/.
23*4882a593Smuzhiyun *
24*4882a593Smuzhiyun * This file may also be available under a different license from Cavium.
25*4882a593Smuzhiyun * Contact Cavium Networks for more information
26*4882a593Smuzhiyun ***********************license end**************************************/
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun /**
29*4882a593Smuzhiyun *
30*4882a593Smuzhiyun * Fixes and workaround for Octeon chip errata. This file
31*4882a593Smuzhiyun * contains functions called by cvmx-helper to workaround known
32*4882a593Smuzhiyun * chip errata. For the most part, code doesn't need to call
33*4882a593Smuzhiyun * these functions directly.
34*4882a593Smuzhiyun *
35*4882a593Smuzhiyun */
36*4882a593Smuzhiyun #include <linux/export.h>
37*4882a593Smuzhiyun
38*4882a593Smuzhiyun #include <asm/octeon/octeon.h>
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun #include <asm/octeon/cvmx-helper-jtag.h>
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun /**
43*4882a593Smuzhiyun * Due to errata G-720, the 2nd order CDR circuit on CN52XX pass
44*4882a593Smuzhiyun * 1 doesn't work properly. The following code disables 2nd order
45*4882a593Smuzhiyun * CDR for the specified QLM.
46*4882a593Smuzhiyun *
47*4882a593Smuzhiyun * @qlm: QLM to disable 2nd order CDR for.
48*4882a593Smuzhiyun */
__cvmx_helper_errata_qlm_disable_2nd_order_cdr(int qlm)49*4882a593Smuzhiyun void __cvmx_helper_errata_qlm_disable_2nd_order_cdr(int qlm)
50*4882a593Smuzhiyun {
51*4882a593Smuzhiyun int lane;
52*4882a593Smuzhiyun cvmx_helper_qlm_jtag_init();
53*4882a593Smuzhiyun /* We need to load all four lanes of the QLM, a total of 1072 bits */
54*4882a593Smuzhiyun for (lane = 0; lane < 4; lane++) {
55*4882a593Smuzhiyun /*
56*4882a593Smuzhiyun * Each lane has 268 bits. We need to set
57*4882a593Smuzhiyun * cfg_cdr_incx<67:64> = 3 and cfg_cdr_secord<77> =
58*4882a593Smuzhiyun * 1. All other bits are zero. Bits go in LSB first,
59*4882a593Smuzhiyun * so start off with the zeros for bits <63:0>.
60*4882a593Smuzhiyun */
61*4882a593Smuzhiyun cvmx_helper_qlm_jtag_shift_zeros(qlm, 63 - 0 + 1);
62*4882a593Smuzhiyun /* cfg_cdr_incx<67:64>=3 */
63*4882a593Smuzhiyun cvmx_helper_qlm_jtag_shift(qlm, 67 - 64 + 1, 3);
64*4882a593Smuzhiyun /* Zeros for bits <76:68> */
65*4882a593Smuzhiyun cvmx_helper_qlm_jtag_shift_zeros(qlm, 76 - 68 + 1);
66*4882a593Smuzhiyun /* cfg_cdr_secord<77>=1 */
67*4882a593Smuzhiyun cvmx_helper_qlm_jtag_shift(qlm, 77 - 77 + 1, 1);
68*4882a593Smuzhiyun /* Zeros for bits <267:78> */
69*4882a593Smuzhiyun cvmx_helper_qlm_jtag_shift_zeros(qlm, 267 - 78 + 1);
70*4882a593Smuzhiyun }
71*4882a593Smuzhiyun cvmx_helper_qlm_jtag_update(qlm);
72*4882a593Smuzhiyun }
73*4882a593Smuzhiyun EXPORT_SYMBOL(__cvmx_helper_errata_qlm_disable_2nd_order_cdr);
74