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/rk3399_rockchip-uboot/arch/x86/lib/
H A Dmrccache.c22 struct mrc_data_container *cache) in next_mrc_block() argument
25 u32 mrc_size = sizeof(*cache) + cache->data_size; in next_mrc_block()
26 u8 *region_ptr = (u8 *)cache; in next_mrc_block()
38 static int is_mrc_cache(struct mrc_data_container *cache) in is_mrc_cache() argument
40 return cache && (cache->signature == MRC_DATA_SIGNATURE); in is_mrc_cache()
45 struct mrc_data_container *cache, *next; in mrccache_find_current() local
51 cache = NULL; in mrccache_find_current()
57 cache = next; in mrccache_find_current()
64 debug("%s: No valid MRC cache found.\n", __func__); in mrccache_find_current()
69 if (cache->checksum != compute_ip_checksum(cache->data, in mrccache_find_current()
[all …]
/rk3399_rockchip-uboot/doc/
H A DREADME.arm-caches1 Disabling I-cache:
4 Disabling D-cache:
7 Enabling I-cache:
10 Enabling D-cache:
14 - Implement enable_caches() for your platform and enable the I-cache and
15 D-cache from this function. This function is called immediately
18 Guidelines for Working with D-cache:
26 lines from the DMA buffer in the cache, subsequent cache-line replacements
27 may corrupt the buffer in memory while the DMA is still going on. Cache-line
29 into the cache while the DMA is going on.
[all …]
H A DREADME.mips19 * Cache incoherency issue caused by do_bootelf_exec() at cmd_elf.c
21 Cache will be disabled before entering the loaded ELF image without
22 writing back and invalidating cache lines. This leads to cache
24 re-initializes the cache. The more common uImage 'bootm' command does
27 [workaround] To avoid this cache incoherency,
29 2) fix dcache_disable() to do both flushing and disabling cache.
38 * Probe CPU types, I-/D-cache and TLB size etc. automatically
40 * Secondary cache support missing
48 * Due to cache initialization issues, the DRAM on board must be
49 initialized in board specific assembler language before the cache init
H A DREADME.fuse20 volatile shadow cache.
29 Read fuse words from the shadow cache.
33 Sense - i.e. read directly from the fusebox, skipping the shadow cache -
34 fuse words. This operation does not update the shadow cache.
42 irreversible. The shadow cache is updated accordingly or not, depending on
53 Override fuse words in the shadow cache.
55 The fusebox is unaffected, so following this operation, the shadow cache
57 used to get the values from the shadow cache or from the fusebox.
H A DREADME.POST35 o) Cache test
276 "Cache test", "cache", \
277 " This test verifies the CPU cache operation.", \
307 cache - cache test
317 => diag cpu cache
320 cache - cache test
321 This test verifies the CPU cache operation.
413 o) Cache test
415 This test will verify the CPU cache (L1 cache). The test will
538 2.2.1.3. Cache test
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/rk3399_rockchip-uboot/arch/arm/cpu/armv7m/
H A Dcache.c13 /* Cache maintenance operation registers */
48 INVALIDATE_POU, /* i-cache invalidate by address */
49 INVALIDATE_POC, /* d-cache invalidate by address */
50 INVALIDATE_SET_WAY, /* d-cache invalidate by sets/ways */
51 FLUSH_POU, /* d-cache clean by address to the PoU */
52 FLUSH_POC, /* d-cache clean by address to the PoC */
53 FLUSH_SET_WAY, /* d-cache clean by sets/ways */
54 FLUSH_INVAL_POC, /* d-cache clean & invalidate by addr to PoC */
55 FLUSH_INVAL_SET_WAY, /* d-cache clean & invalidate by set/ways */
64 static void get_cache_ways_sets(struct dcache_config *cache) in get_cache_ways_sets() argument
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/rk3399_rockchip-uboot/arch/arm/cpu/armv7/
H A Dcache_v7_asm.S21 * Flush the whole D-cache.
25 * Note: copied from arch/arm/mm/cache-v7.S of Linux 4.4
34 mov r10, #0 @ start clean at cache level 0
36 add r2, r10, r10, lsr #1 @ work out 3x current cache level
37 mov r1, r0, lsr r2 @ extract cache type bits from clidr
38 and r1, r1, #7 @ mask of the bits for current cache only
39 cmp r1, #2 @ see what cache we have at this level
40 blt skip @ skip if no cache, or just i-cache
41 mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
44 and r2, r1, #7 @ extract the length of the cache lines
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H A Dcpu.c21 #include <asm/cache.h>
42 * turn off D-cache in cleanup_before_linux_select()
43 * dcache_disable() in turn flushes the d-cache and disables MMU in cleanup_before_linux_select()
49 * After D-cache is flushed and before it is disabled there may in cleanup_before_linux_select()
50 * be some new valid entries brought into the cache. We are in cleanup_before_linux_select()
55 * any static data) So just invalidate the entire d-cache again in cleanup_before_linux_select()
64 * Turn off I-cache and invalidate it in cleanup_before_linux_select()
75 * Some CPU need more cache attention before starting the kernel. in cleanup_before_linux_select()
H A Dcache_v7.c26 /* Read current CP15 Cache Size ID Register */ in get_ccsidr()
35 /* Align start to cache line boundary */ in v7_dcache_clean_inval_range()
38 /* DCCIMVAC - Clean & Invalidate data cache by MVA to PoC */ in v7_dcache_clean_inval_range()
65 /* DCIMVAC - Invalidate data cache by MVA to PoC */ in v7_dcache_inval_range()
118 * Performs a clean & invalidation of the entire data cache
129 * Invalidates range in all levels of D-cache/unified cache used:
143 * Flush range(clean & invalidate) from all levels of D-cache/unified
144 * cache used:
200 /* Invalidate entire I-cache and branch predictor array */
205 * Also flushes branch target cache. in invalidate_icache_all()
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/rk3399_rockchip-uboot/drivers/crypto/rockchip/
H A Dcrypto_hash_cache.c18 if (!hash_cache->cache) { in hash_cache_calc()
19 hash_cache->cache = (u8 *)memalign(CONFIG_SYS_CACHELINE_SIZE, in hash_cache_calc()
21 if (!hash_cache->cache) in hash_cache_calc()
31 /* copy to cache */ in hash_cache_calc()
32 debug("%s, %d: copy to cache %u\n", in hash_cache_calc()
34 memcpy(hash_cache->cache + hash_cache->cache_size, data, in hash_cache_calc()
38 /* if last one calc cache immediately */ in hash_cache_calc()
40 debug("%s, %d: last one calc cache %u\n", in hash_cache_calc()
45 hash_cache->cache, in hash_cache_calc()
55 /* 1. make cache be full */ in hash_cache_calc()
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/rk3399_rockchip-uboot/arch/powerpc/cpu/mpc86xx/
H A Dcache.S7 #include <asm/cache.h>
23 # error "Invalid cache line size!"
27 * Most of this code is taken from 74xx_7xx/cache.S
32 * Invalidate L1 instruction cache.
43 * Invalidate L1 data cache.
53 * Flush data cache.
68 * Write any modified data cache blocks out to memory
69 * and invalidate the corresponding instruction cache blocks.
95 * Write any modified data cache blocks out to memory.
96 * Does not invalidate the corresponding cache lines (especially for
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/rk3399_rockchip-uboot/arch/powerpc/include/asm/
H A Dcache.h2 * include/asm-ppc/cache.h
9 /* bytes per L1 cache line */
23 * Use the L1 data cache line size value for the minimum DMA buffer alignment
67 #define CACHECRBA 0x80000823 /* Cache configuration register address */
68 #define L2CACHE_MASK 0x03 /* Mask for 2 L2 Cache bits */
73 #define L2CACHE_PARITY 0x08 /* Mask for L2 Cache Parity Protected bit */
76 /* Cache control on the MPC8xx is provided through some additional
79 #define IC_CST 560 /* Instruction cache control/status */
82 #define DC_CST 568 /* Data cache control/status */
86 /* Commands. Only the first few are available to the instruction cache.
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/rk3399_rockchip-uboot/arch/nds32/include/asm/
H A Dcache.h12 /* cache */
34 /* I-cache sets (# of cache lines) per way */
36 /* I-cache ways */
40 /* D-cache sets (# of cache lines) per way */
42 /* D-cache ways */
46 /* I-cache line size */
49 /* D-cache line size */
54 * The current upper bound for NDS32 L1 data cache line sizes is 32 bytes.
56 * specified an alternate cache line size.
/rk3399_rockchip-uboot/arch/arm/cpu/armv8/
H A Dcache.S19 * flush or invalidate one level cache.
21 * x0: cache level
28 msr csselr_el1, x12 /* select cache level */
31 and x2, x6, #7 /* x2 <- log2(cache line size)-4 */
32 add x2, x2, #4 /* x2 <- log2(cache line size) */
38 /* x12 <- cache level << 1 */
40 /* x3 <- number of cache ways - 1 */
41 /* x4 <- number of cache sets - 1 */
69 * flush or invalidate all data cache by SET/WAY.
80 mov x0, #0 /* start flush at cache level 0 */
[all …]
/rk3399_rockchip-uboot/drivers/block/
H A Dblkcache.c22 char *cache; member
61 const char *src = node->cache + (start - node->start) * blksz; in blkcache_read()
82 /* don't cache big stuff */ in blkcache_fill()
98 free(node->cache); in blkcache_fill()
99 node->cache = 0; in blkcache_fill()
105 node->cache = 0; in blkcache_fill()
108 if (!node->cache) { in blkcache_fill()
109 node->cache = malloc(bytes); in blkcache_fill()
110 if (!node->cache) { in blkcache_fill()
124 memcpy(node->cache, buffer, bytes); in blkcache_fill()
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/rk3399_rockchip-uboot/arch/x86/cpu/quark/
H A Ddram.c22 struct mrc_data_container *cache; in prepare_mrc_cache() local
30 cache = mrccache_find_current(&entry); in prepare_mrc_cache()
31 if (!cache) in prepare_mrc_cache()
34 debug("%s: mrc cache at %p, size %x checksum %04x\n", __func__, in prepare_mrc_cache()
35 cache->data, cache->data_size, cache->checksum); in prepare_mrc_cache()
37 /* copy mrc cache to the mrc_params */ in prepare_mrc_cache()
38 memcpy(&mrc_params->timings, cache->data, cache->data_size); in prepare_mrc_cache()
128 char *cache; in dram_init() local
154 cache = malloc(sizeof(struct mrc_timings)); in dram_init()
155 if (cache) { in dram_init()
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/rk3399_rockchip-uboot/arch/arm/mach-uniphier/arm32/
H A Dcache-uniphier.c15 #include "cache-uniphier.h"
23 #define UNIPHIER_SSCC_ON (0x1 << 0) /* enable cache */
31 #define UNIPHIER_SSCOPE 0x506c0244 /* Cache Operation Primitive Entry */
52 #define UNIPHIER_SSCOQM_CM_PREFETCH 0x3 /* prefetch to cache */
57 #define UNIPHIER_SSCOQAD 0x506c024c /* Cache Operation Queue Address */
58 #define UNIPHIER_SSCOQSZ 0x506c0250 /* Cache Operation Queue Size */
59 #define UNIPHIER_SSCOQMASK 0x506c0254 /* Cache Operation Queue Address Mask */
60 #define UNIPHIER_SSCOQWN 0x506c0258 /* Cache Operation Queue Way Number */
61 #define UNIPHIER_SSCOPPQSEF 0x506c025c /* Cache Operation Queue Set Complete */
64 #define UNIPHIER_SSCOLPQS 0x506c0260 /* Cache Operation Queue Status */
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/rk3399_rockchip-uboot/arch/arm/lib/
H A Dcache-pl310.c55 /* PL310 currently supports only 32 bytes cache line */ in v7_outer_cache_flush_range()
59 * Align to the beginning of cache-line - this ensures that in v7_outer_cache_flush_range()
73 /* PL310 currently supports only 32 bytes cache line */ in v7_outer_cache_inval_range()
77 * If start address is not aligned to cache-line do not in v7_outer_cache_inval_range()
78 * invalidate the first cache-line in v7_outer_cache_inval_range()
83 /* move to next cache line */ in v7_outer_cache_inval_range()
88 * If stop address is not aligned to cache-line do not in v7_outer_cache_inval_range()
89 * invalidate the last cache-line in v7_outer_cache_inval_range()
94 /* align to the beginning of this cache line */ in v7_outer_cache_inval_range()
/rk3399_rockchip-uboot/arch/mips/lib/
H A Dcache_init.S2 * Cache-handling routined for MIPS CPUs
46 10: cache \op, 0(\curr)
95 * To initialise the instruction cache it is essential that a source of data
120 * then we proceed knowing there's no L2 cache.
130 * From MIPSr6 onwards the L2 cache configuration might not be reported
171 /* Bypass the L2 cache so that we can init the L1s early */
193 * cache configuration from the cop0 Config2 register.
244 /* Determine the largest L1 cache size */
270 * rest of the cache initialisation using the L1 instruction cache.
277 1: cache INDEX_STORE_TAG_SD, 0(t0)
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/rk3399_rockchip-uboot/arch/x86/lib/fsp/
H A Dfsp_common.c89 struct mrc_data_container *cache; in fsp_prepare_mrc_cache() local
97 cache = mrccache_find_current(&entry); in fsp_prepare_mrc_cache()
98 if (!cache) in fsp_prepare_mrc_cache()
101 debug("%s: mrc cache at %p, size %x checksum %04x\n", __func__, in fsp_prepare_mrc_cache()
102 cache->data, cache->data_size, cache->checksum); in fsp_prepare_mrc_cache()
104 return cache->data; in fsp_prepare_mrc_cache()
153 /* If waking from S3 and no cache then */ in arch_fsp_init()
154 debug("No MRC cache found in S3 resume path\n"); in arch_fsp_init()
/rk3399_rockchip-uboot/arch/x86/cpu/intel_common/
H A Dcar.S28 /* Cache 4GB - MRC_SIZE_KB for MRC */
81 /* Set Cache-as-RAM base address */
88 /* Set Cache-as-RAM mask */
102 /* Enable cache (CR0.CD = 0, CR0.NW = 0) */
115 /* Clear the cache memory region. This will also fill up the cache */
129 /* Enable Cache-as-RAM mode by disabling cache */
134 /* Enable cache for our code in Flash because we do XIP here */
161 /* Enable cache */
179 /* Disable cache */
204 /* Clear the MTRR that was used to cache MRC */
/rk3399_rockchip-uboot/arch/arm/mach-omap2/
H A Domap-cache.c16 #include <asm/cache.h>
22 * Set C - Cache Bit3
28 * With LPAE cache configuration happens via MAIR0 register
30 * 0xFF maps to Cache writeback with Read and Write Allocate set
47 /* Enable D-cache. I-cache is already enabled in start.S */ in enable_caches()
/rk3399_rockchip-uboot/arch/powerpc/cpu/mpc85xx/
H A Dfdt.c170 fdt_setprop(blob, off, "cache-unified", NULL, 0); in ft_fixup_l3cache()
171 fdt_setprop_cell(blob, off, "cache-block-size", line_size); in ft_fixup_l3cache()
172 fdt_setprop_cell(blob, off, "cache-size", size); in ft_fixup_l3cache()
173 fdt_setprop_cell(blob, off, "cache-sets", num_sets); in ft_fixup_l3cache()
174 fdt_setprop_cell(blob, off, "cache-level", 3); in ft_fixup_l3cache()
176 fdt_setprop_cell(blob, off, "cache-stash-id", 1); in ft_fixup_l3cache()
196 len = sprintf(buf, "fsl,mpc%s-l2-cache-controller", in ft_fixup_l2cache_compatible()
200 len = sprintf(buf, "fsl,%c%s-l2-cache-controller", in ft_fixup_l2cache_compatible()
205 * append "cache" after the NULL character that the previous in ft_fixup_l2cache_compatible()
209 len += sprintf(buf + len, "cache") + 1; in ft_fixup_l2cache_compatible()
[all …]
/rk3399_rockchip-uboot/arch/x86/include/asm/
H A Dmrccache.h34 * mrccache_find_current() - find the latest MRC cache record
36 * This searches the MRC cache region looking for the latest record to use
39 * @entry: Position and size of MRC cache in SPI flash
45 * mrccache_update() - update the MRC cache with a new record
47 * This writes a new record to the end of the MRC cache region. If the new
51 * @entry: Position and size of MRC cache in SPI flash
67 * when MRC cache is enabled.
89 * @entry: Position and size of MRC cache in SPI flash
/rk3399_rockchip-uboot/arch/arm/include/asm/
H A Darm32_macros.S119 /* Instruction cache invalidate by MVA */
129 /* Data cache invalidate by MVA */
134 /* Data cache invalidate by set/way */
139 /* Data cache clean by MVA */
144 /* Data cache clean by set/way */
149 /* Data cache invalidate by MVA */
154 /* Data cache clean and invalidate by set/way */
235 /* Cache Level ID Register */
240 /* Cache Size ID Registers */
245 /* Cache Size Selection Register */

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