History log of /rk3399_rockchip-uboot/arch/arm/mach-uniphier/arm32/cache-uniphier.c (Results 1 – 12 of 12)
Revision Date Author Comments
# 8197d928 21-Aug-2017 Tom Rini <trini@konsulko.com>

Merge git://git.denx.de/u-boot-uniphier

- Fix unmet direct dependencies warning
- Remove old sLD3 SoC support
- Update reset data
- Add dr_mode DT property to avoid warning


# 00aa453e 13-Aug-2017 Masahiro Yamada <yamada.masahiro@socionext.com>

ARM: uniphier: remove sLD3 SoC support

This SoC is too old. It is difficult to maintain any longer.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>


# 28cd88ba 11-Aug-2016 Tom Rini <trini@konsulko.com>

Merge branch 'master' of git://git.denx.de/u-boot-uniphier


# ee9bc77f 10-Aug-2016 Masahiro Yamada <yamada.masahiro@socionext.com>

ARM: uniphier: add uniphier_cache_set_active_ways()

This outer cache allows to control active ways independently for
each CPU, so this function will be useful to set up active ways
for a specific CP

ARM: uniphier: add uniphier_cache_set_active_ways()

This outer cache allows to control active ways independently for
each CPU, so this function will be useful to set up active ways
for a specific CPU.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

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# 59416380 10-Aug-2016 Masahiro Yamada <yamada.masahiro@socionext.com>

ARM: uniphier: add uniphier_cache_inv_way() to support way invalidation

This invalidates entries in specified ways of the outer cache.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>


# 7382d178 10-Aug-2016 Masahiro Yamada <yamada.masahiro@socionext.com>

ARM: uniphier: move (and rename) CONFIG_UNIPHIER_L2CACHE_ON to Kconfig

Move this option to Kconfig, renaming it into CONFIG_CACHE_UNIPHIER.
The new option name makes sense enough, and the same as Li

ARM: uniphier: move (and rename) CONFIG_UNIPHIER_L2CACHE_ON to Kconfig

Move this option to Kconfig, renaming it into CONFIG_CACHE_UNIPHIER.
The new option name makes sense enough, and the same as Linux has.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

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# 95646e1d 10-Aug-2016 Masahiro Yamada <yamada.masahiro@socionext.com>

ARM: uniphier: move outer cache register macros to .c file

Now, all of these macros are only used in cache-uniphier.c, so
there is no need to export them in a header file.

Signed-off-by: Masahiro Y

ARM: uniphier: move outer cache register macros to .c file

Now, all of these macros are only used in cache-uniphier.c, so
there is no need to export them in a header file.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

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# 6f579db7 10-Aug-2016 Masahiro Yamada <yamada.masahiro@socionext.com>

ARM: uniphier: export uniphier_cache_enable/disable functions

The System Cache (outer cache) is used not only as L2 cache,
but also as locked SRAM. The functions for turning on/off it
is necessary

ARM: uniphier: export uniphier_cache_enable/disable functions

The System Cache (outer cache) is used not only as L2 cache,
but also as locked SRAM. The functions for turning on/off it
is necessary whether the L2 cache is enabled or not.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

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# e731a538 10-Aug-2016 Masahiro Yamada <yamada.masahiro@socionext.com>

ARM: uniphier: do not compile v7_outer_cache_disable if L2 is disabled

If CONFIG_UNIPHIER_L2CACHE_ON is undefined, the L2 cache is never
enabled, so there is no need for v7_outer_cache_disable(). T

ARM: uniphier: do not compile v7_outer_cache_disable if L2 is disabled

If CONFIG_UNIPHIER_L2CACHE_ON is undefined, the L2 cache is never
enabled, so there is no need for v7_outer_cache_disable(). The weak
stub avoids the compile error anyway.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

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# 95a1feca 10-Aug-2016 Masahiro Yamada <yamada.masahiro@socionext.com>

ARM: uniphier: support prefetch and touch operations for outer cache

The UniPhier outer cache (L2 cache on ARMv7 SoCs) can be used as
SRAM by locking ways.

These functions will be used to transfer

ARM: uniphier: support prefetch and touch operations for outer cache

The UniPhier outer cache (L2 cache on ARMv7 SoCs) can be used as
SRAM by locking ways.

These functions will be used to transfer the trampoline code for SMP
into the locked SRAM.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

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# 3ffc7475 10-Aug-2016 Masahiro Yamada <yamada.masahiro@socionext.com>

ARM: uniphier: refactor outer cache code

Unify the range/all operation routines into the common function,
uniphier_cache_maint_common(), and sync code with Linux a bit more.

This reduces the code d

ARM: uniphier: refactor outer cache code

Unify the range/all operation routines into the common function,
uniphier_cache_maint_common(), and sync code with Linux a bit more.

This reduces the code duplication.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

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# 4bab70a7 22-Jul-2016 Masahiro Yamada <yamada.masahiro@socionext.com>

ARM: uniphier: rename outer-cache register macros

Sync register macros with Linux code. This will be helpful to
develop the counterpart of Linux.

Signed-off-by: Masahiro Yamada <yamada.masahiro@so

ARM: uniphier: rename outer-cache register macros

Sync register macros with Linux code. This will be helpful to
develop the counterpart of Linux.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

show more ...