1*983e3700STom Rini /* 2*983e3700STom Rini * 3*983e3700STom Rini * Common functions for OMAP4/5 based boards 4*983e3700STom Rini * 5*983e3700STom Rini * (C) Copyright 2010 6*983e3700STom Rini * Texas Instruments, <www.ti.com> 7*983e3700STom Rini * 8*983e3700STom Rini * Author : 9*983e3700STom Rini * Aneesh V <aneesh@ti.com> 10*983e3700STom Rini * Steve Sakoman <steve@sakoman.com> 11*983e3700STom Rini * 12*983e3700STom Rini * SPDX-License-Identifier: GPL-2.0+ 13*983e3700STom Rini */ 14*983e3700STom Rini 15*983e3700STom Rini #include <common.h> 16*983e3700STom Rini #include <asm/cache.h> 17*983e3700STom Rini 18*983e3700STom Rini DECLARE_GLOBAL_DATA_PTR; 19*983e3700STom Rini 20*983e3700STom Rini /* 21*983e3700STom Rini * Without LPAE short descriptors are used 22*983e3700STom Rini * Set C - Cache Bit3 23*983e3700STom Rini * Set B - Buffer Bit2 24*983e3700STom Rini * The last 2 bits set to 0b10 25*983e3700STom Rini * Do Not set XN bit4 26*983e3700STom Rini * So value is 0xe 27*983e3700STom Rini * 28*983e3700STom Rini * With LPAE cache configuration happens via MAIR0 register 29*983e3700STom Rini * AttrIndx value is 0x3 for picking byte3 for MAIR0 which has 0xFF. 30*983e3700STom Rini * 0xFF maps to Cache writeback with Read and Write Allocate set 31*983e3700STom Rini * The bits[1:0] should have the value 0b01 for the first level 32*983e3700STom Rini * descriptor. 33*983e3700STom Rini * So the value is 0xd 34*983e3700STom Rini */ 35*983e3700STom Rini 36*983e3700STom Rini #ifdef CONFIG_ARMV7_LPAE 37*983e3700STom Rini #define ARMV7_DCACHE_POLICY DCACHE_WRITEALLOC 38*983e3700STom Rini #else 39*983e3700STom Rini #define ARMV7_DCACHE_POLICY DCACHE_WRITEBACK & ~TTB_SECT_XN_MASK 40*983e3700STom Rini #endif 41*983e3700STom Rini 42*983e3700STom Rini #define ARMV7_DOMAIN_CLIENT 1 43*983e3700STom Rini #define ARMV7_DOMAIN_MASK (0x3 << 0) 44*983e3700STom Rini enable_caches(void)45*983e3700STom Rinivoid enable_caches(void) 46*983e3700STom Rini { 47*983e3700STom Rini /* Enable D-cache. I-cache is already enabled in start.S */ 48*983e3700STom Rini dcache_enable(); 49*983e3700STom Rini } 50*983e3700STom Rini dram_bank_mmu_setup(int bank)51*983e3700STom Rinivoid dram_bank_mmu_setup(int bank) 52*983e3700STom Rini { 53*983e3700STom Rini bd_t *bd = gd->bd; 54*983e3700STom Rini int i; 55*983e3700STom Rini 56*983e3700STom Rini u32 start = bd->bi_dram[bank].start >> MMU_SECTION_SHIFT; 57*983e3700STom Rini u32 size = bd->bi_dram[bank].size >> MMU_SECTION_SHIFT; 58*983e3700STom Rini u32 end = start + size; 59*983e3700STom Rini 60*983e3700STom Rini debug("%s: bank: %d\n", __func__, bank); 61*983e3700STom Rini for (i = start; i < end; i++) 62*983e3700STom Rini set_section_dcache(i, ARMV7_DCACHE_POLICY); 63*983e3700STom Rini } 64*983e3700STom Rini arm_init_domains(void)65*983e3700STom Rinivoid arm_init_domains(void) 66*983e3700STom Rini { 67*983e3700STom Rini u32 reg; 68*983e3700STom Rini 69*983e3700STom Rini reg = get_dacr(); 70*983e3700STom Rini /* 71*983e3700STom Rini * Set DOMAIN to client access so that all permissions 72*983e3700STom Rini * set in pagetables are validated by the mmu. 73*983e3700STom Rini */ 74*983e3700STom Rini reg &= ~ARMV7_DOMAIN_MASK; 75*983e3700STom Rini reg |= ARMV7_DOMAIN_CLIENT; 76*983e3700STom Rini set_dacr(reg); 77*983e3700STom Rini } 78