Lines Matching full:cache

2  *  Cache-handling routined for MIPS CPUs
46 10:	cache		\op, 0(\curr)
95  * To initialise the instruction cache it is essential that a source of data
120 	 * then we proceed knowing there's no L2 cache.
130 	 * From MIPSr6 onwards the L2 cache configuration might not be reported
171 	/* Bypass the L2 cache so that we can init the L1s early */
193 	 * cache configuration from the cop0 Config2 register.
244 	/* Determine the largest L1 cache size */
270 	 * rest of the cache initialisation using the L1 instruction cache.
277 1:	cache		INDEX_STORE_TAG_SD, 0(t0)
304 	 * parity for the cache.
308 	 * Initialize the I-cache first,
324 	/* Enable use of the I-cache by setting Config.K0 */
338 	 * then initialize D-cache.
423 	/* Ensure all cache operations complete before returning */
429  * dcache_status - get cache status
431  * RETURNS: 0 - cache disabled; 1 - cache enabled
445  * dcache_disable - disable cache
460  * dcache_enable - enable cache