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/OK3568_Linux_fs/kernel/sound/pci/au88x0/
H A Dau88x0_xtalk.c248 hwwrite(vortex->mmio, 0x24200 + i * 0x24, coefs[i][0]); in vortex_XtalkHw_SetLeftEQ()
249 hwwrite(vortex->mmio, 0x24204 + i * 0x24, coefs[i][1]); in vortex_XtalkHw_SetLeftEQ()
250 hwwrite(vortex->mmio, 0x24208 + i * 0x24, coefs[i][2]); in vortex_XtalkHw_SetLeftEQ()
251 hwwrite(vortex->mmio, 0x2420c + i * 0x24, coefs[i][3]); in vortex_XtalkHw_SetLeftEQ()
252 hwwrite(vortex->mmio, 0x24210 + i * 0x24, coefs[i][4]); in vortex_XtalkHw_SetLeftEQ()
254 hwwrite(vortex->mmio, 0x24538, arg_0 & 0xffff); in vortex_XtalkHw_SetLeftEQ()
255 hwwrite(vortex->mmio, 0x2453C, arg_4 & 0xffff); in vortex_XtalkHw_SetLeftEQ()
265 hwwrite(vortex->mmio, 0x242b4 + i * 0x24, coefs[i][0]); in vortex_XtalkHw_SetRightEQ()
266 hwwrite(vortex->mmio, 0x242b8 + i * 0x24, coefs[i][1]); in vortex_XtalkHw_SetRightEQ()
267 hwwrite(vortex->mmio, 0x242bc + i * 0x24, coefs[i][2]); in vortex_XtalkHw_SetRightEQ()
[all …]
H A Dau88x0_core.c79 hwwrite(vortex->mmio, VORTEX_MIXER_SR, in vortex_mixer_en_sr()
80 hwread(vortex->mmio, VORTEX_MIXER_SR) | (0x1 << channel)); in vortex_mixer_en_sr()
84 hwwrite(vortex->mmio, VORTEX_MIXER_SR, in vortex_mixer_dis_sr()
85 hwread(vortex->mmio, VORTEX_MIXER_SR) & ~(0x1 << channel)); in vortex_mixer_dis_sr()
93 hwwrite(vortex->mmio, VORTEX_MIX_INVOL_A + ((mix << 5) + channel),
95 hwwrite(vortex->mmio, VORTEX_MIX_INVOL_B + ((mix << 5) + channel),
102 a = hwread(vortex->mmio, VORTEX_MIX_VOL_A + (mix << 2)) & 0xff;
114 a = hwread(vortex->mmio,
139 a = hwread(vortex->mmio,
143 hwwrite(vortex->mmio,
[all …]
H A Dau88x0_eq.c41 hwwrite(vortex->mmio, 0x2b3c4, gain); in vortex_EqHw_SetTimeConsts()
42 hwwrite(vortex->mmio, 0x2b3c8, level); in vortex_EqHw_SetTimeConsts()
60 hwwrite(vortex->mmio, 0x2b000 + n * 0x30, coefs[i + 0]); in vortex_EqHw_SetLeftCoefs()
61 hwwrite(vortex->mmio, 0x2b004 + n * 0x30, coefs[i + 1]); in vortex_EqHw_SetLeftCoefs()
64 hwwrite(vortex->mmio, 0x2b008 + n * 0x30, coefs[i + 2]); in vortex_EqHw_SetLeftCoefs()
65 hwwrite(vortex->mmio, 0x2b00c + n * 0x30, coefs[i + 3]); in vortex_EqHw_SetLeftCoefs()
66 hwwrite(vortex->mmio, 0x2b010 + n * 0x30, coefs[i + 4]); in vortex_EqHw_SetLeftCoefs()
68 hwwrite(vortex->mmio, 0x2b008 + n * 0x30, sign_invert(coefs[2 + i])); in vortex_EqHw_SetLeftCoefs()
69 hwwrite(vortex->mmio, 0x2b00c + n * 0x30, sign_invert(coefs[3 + i])); in vortex_EqHw_SetLeftCoefs()
70 hwwrite(vortex->mmio, 0x2b010 + n * 0x30, sign_invert(coefs[4 + i])); in vortex_EqHw_SetLeftCoefs()
[all …]
H A Dau88x0_synth.c32 //temp = hwread(vortex->mmio, 0x80 + ((wt >> 0x5)<< 0xf) + (((wt & 0x1f) >> 1) << 2)); in vortex_wt_setstereo()
33 temp = hwread(vortex->mmio, WT_STEREO(wt)); in vortex_wt_setstereo()
35 //hwwrite(vortex->mmio, 0x80 + ((wt >> 0x5)<< 0xf) + (((wt & 0x1f) >> 1) << 2), temp); in vortex_wt_setstereo()
36 hwwrite(vortex->mmio, WT_STEREO(wt), temp); in vortex_wt_setstereo()
45 temp = hwread(vortex->mmio, WT_DSREG((wt >= 0x20) ? 1 : 0)); in vortex_wt_setdsout()
50 hwwrite(vortex->mmio, WT_DSREG((wt >= 0x20) ? 1 : 0), temp); in vortex_wt_setdsout()
70 hwwrite(vortex->mmio, WT_SRAMP(0), 0x880000); in vortex_wt_allocroute()
71 //hwwrite(vortex->mmio, WT_GMODE(0), 0xffffffff); in vortex_wt_allocroute()
73 hwwrite(vortex->mmio, WT_SRAMP(1), 0x880000); in vortex_wt_allocroute()
74 //hwwrite(vortex->mmio, WT_GMODE(1), 0xffffffff); in vortex_wt_allocroute()
[all …]
H A Dau88x0_mpu401.c16 /* Check for mpu401 mmio support. */
42 (hwread(vortex->mmio, VORTEX_CTRL) & ~CTRL_MIDI_PORT) | in snd_vortex_midi()
44 hwwrite(vortex->mmio, VORTEX_CTRL, temp); in snd_vortex_midi()
48 (hwread(vortex->mmio, VORTEX_CTRL) & ~CTRL_MIDI_PORT) & in snd_vortex_midi()
50 hwwrite(vortex->mmio, VORTEX_CTRL, temp); in snd_vortex_midi()
54 temp = hwread(vortex->mmio, VORTEX_CTRL2) & 0xffff00cf; in snd_vortex_midi()
56 hwwrite(vortex->mmio, VORTEX_CTRL2, temp); in snd_vortex_midi()
57 hwwrite(vortex->mmio, VORTEX_MIDI_CMD, MPU401_RESET); in snd_vortex_midi()
60 temp = hwread(vortex->mmio, VORTEX_MIDI_DATA); in snd_vortex_midi()
66 hwwrite(vortex->mmio, VORTEX_IRQ_CTRL, in snd_vortex_midi()
[all …]
H A Dau88x0_a3d.c25 hwwrite(vortex->mmio, in a3dsrc_SetTimeConsts()
27 hwwrite(vortex->mmio, in a3dsrc_SetTimeConsts()
29 hwwrite(vortex->mmio, in a3dsrc_SetTimeConsts()
31 hwwrite(vortex->mmio, in a3dsrc_SetTimeConsts()
51 hwwrite(vortex->mmio, in a3dsrc_SetAtmosTarget()
54 hwwrite(vortex->mmio, in a3dsrc_SetAtmosTarget()
57 hwwrite(vortex->mmio, in a3dsrc_SetAtmosTarget()
66 hwwrite(vortex->mmio, in a3dsrc_SetAtmosCurrent()
69 hwwrite(vortex->mmio, in a3dsrc_SetAtmosCurrent()
72 hwwrite(vortex->mmio, in a3dsrc_SetAtmosCurrent()
[all …]
/OK3568_Linux_fs/kernel/drivers/video/fbdev/i810/
H A Di810_main.c161 * @mmio: address of register space
167 static void i810_screen_off(u8 __iomem *mmio, u8 mode) in i810_screen_off() argument
172 i810_writeb(SR_INDEX, mmio, SR01); in i810_screen_off()
173 val = i810_readb(SR_DATA, mmio); in i810_screen_off()
177 while((i810_readw(DISP_SL, mmio) & 0xFFF) && count--); in i810_screen_off()
178 i810_writeb(SR_INDEX, mmio, SR01); in i810_screen_off()
179 i810_writeb(SR_DATA, mmio, val); in i810_screen_off()
184 * @mmio: address of register space
191 static void i810_dram_off(u8 __iomem *mmio, u8 mode) in i810_dram_off() argument
195 val = i810_readb(DRAMCH, mmio); in i810_dram_off()
[all …]
/OK3568_Linux_fs/kernel/drivers/net/ethernet/amd/
H A Damd8111e.c101 void __iomem *mmio = lp->mmio; in amd8111e_read_phy() local
105 reg_val = readl(mmio + PHY_ACCESS); in amd8111e_read_phy()
107 reg_val = readl( mmio + PHY_ACCESS ); in amd8111e_read_phy()
110 ((reg & 0x1f) << 16), mmio +PHY_ACCESS); in amd8111e_read_phy()
112 reg_val = readl(mmio + PHY_ACCESS); in amd8111e_read_phy()
131 void __iomem *mmio = lp->mmio; in amd8111e_write_phy() local
134 reg_val = readl(mmio + PHY_ACCESS); in amd8111e_write_phy()
136 reg_val = readl( mmio + PHY_ACCESS ); in amd8111e_write_phy()
139 ((reg & 0x1f) << 16)|val, mmio + PHY_ACCESS); in amd8111e_write_phy()
142 reg_val = readl(mmio + PHY_ACCESS); in amd8111e_write_phy()
[all …]
/OK3568_Linux_fs/kernel/drivers/phy/rockchip/
H A Dphy-rockchip-inno-combphy.c83 void __iomem *mmio; member
557 reg = readl(priv->mmio + 0x21a8); in rockchip_combphy_set_mode()
566 writel(reg, priv->mmio + 0x21a8); in rockchip_combphy_set_mode()
662 priv->mmio = devm_ioremap_resource(dev, res); in rockchip_combphy_probe()
663 if (IS_ERR(priv->mmio)) { in rockchip_combphy_probe()
664 ret = PTR_ERR(priv->mmio); in rockchip_combphy_probe()
723 writel(0x00, priv->mmio + 0x2118); in rk1808_combphy_cfg()
724 writel(0x64, priv->mmio + 0x211c); in rk1808_combphy_cfg()
725 writel(0x01, priv->mmio + 0x2020); in rk1808_combphy_cfg()
726 writel(0x64, priv->mmio + 0x2028); in rk1808_combphy_cfg()
[all …]
H A Dphy-rockchip-naneng-combphy.c80 void __iomem *mmio; member
148 val = readl(priv->mmio + (0x19 << 2)); in rockchip_combphy_pcie_init()
150 writel(val, priv->mmio + (0x19 << 2)); in rockchip_combphy_pcie_init()
402 priv->mmio = devm_ioremap_resource(dev, res); in rockchip_combphy_probe()
403 if (IS_ERR(priv->mmio)) { in rockchip_combphy_probe()
404 ret = PTR_ERR(priv->mmio); in rockchip_combphy_probe()
463 val = readl(priv->mmio + 0x18); in rk3528_combphy_cfg()
466 writel(val, priv->mmio + 0x18); in rk3528_combphy_cfg()
475 val = readl(priv->mmio + 0x18); in rk3528_combphy_cfg()
478 writel(val, priv->mmio + 0x18); in rk3528_combphy_cfg()
[all …]
/OK3568_Linux_fs/kernel/drivers/staging/comedi/drivers/
H A Dni_pcidio.c312 dev->mmio + DMA_LINE_CONTROL_GROUP1); in ni_pcidio_request_di_mite_channel()
328 dev->mmio + DMA_LINE_CONTROL_GROUP1); in ni_pcidio_release_di_mite_channel()
394 status = readb(dev->mmio + INTERRUPT_AND_WINDOW_STATUS); in nidio_interrupt()
395 flags = readb(dev->mmio + GROUP_1_FLAGS); in nidio_interrupt()
409 dev->mmio + MASTER_DMA_AND_INTERRUPT_CONTROL); in nidio_interrupt()
421 writeb(0x00, dev->mmio + in nidio_interrupt()
426 auxdata = readl(dev->mmio + GROUP_1_FIFO); in nidio_interrupt()
428 flags = readb(dev->mmio + GROUP_1_FLAGS); in nidio_interrupt()
433 writeb(CLEAR_EXPIRED, dev->mmio + GROUP_1_SECOND_CLEAR); in nidio_interrupt()
436 writeb(0x00, dev->mmio + OP_MODE); in nidio_interrupt()
[all …]
H A Drtd520.c465 writel(0, dev->mmio + LAS0_CGT_CLEAR); in rtd_load_channelgain_list()
466 writel(1, dev->mmio + LAS0_CGT_ENABLE); in rtd_load_channelgain_list()
469 dev->mmio + LAS0_CGT_WRITE); in rtd_load_channelgain_list()
472 writel(0, dev->mmio + LAS0_CGT_ENABLE); in rtd_load_channelgain_list()
474 dev->mmio + LAS0_CGL_WRITE); in rtd_load_channelgain_list()
489 writel(0, dev->mmio + LAS0_ADC_FIFO_CLEAR); in rtd520_probe_fifo_depth()
492 writel(0, dev->mmio + LAS0_ADC_CONVERSION); in rtd520_probe_fifo_depth()
497 writew(0, dev->mmio + LAS0_ADC); in rtd520_probe_fifo_depth()
499 fifo_status = readl(dev->mmio + LAS0_ADC); in rtd520_probe_fifo_depth()
509 writel(0, dev->mmio + LAS0_ADC_FIFO_CLEAR); in rtd520_probe_fifo_depth()
[all …]
H A Ddt3000.c50 * PCI BAR0 - dual-ported RAM location definitions (dev->mmio)
232 writew(cmd, dev->mmio + DPR_CMD_MBX); in dt3k_send_cmd()
235 status = readw(dev->mmio + DPR_CMD_MBX); in dt3k_send_cmd()
251 writew(subsys, dev->mmio + DPR_SUBSYS); in dt3k_readsingle()
253 writew(chan, dev->mmio + DPR_PARAMS(0)); in dt3k_readsingle()
254 writew(gain, dev->mmio + DPR_PARAMS(1)); in dt3k_readsingle()
258 return readw(dev->mmio + DPR_PARAMS(2)); in dt3k_readsingle()
264 writew(subsys, dev->mmio + DPR_SUBSYS); in dt3k_writesingle()
266 writew(chan, dev->mmio + DPR_PARAMS(0)); in dt3k_writesingle()
267 writew(0, dev->mmio + DPR_PARAMS(1)); in dt3k_writesingle()
[all …]
/OK3568_Linux_fs/kernel/drivers/ata/
H A Dsata_sx4.c442 void __iomem *mmio = ap->host->iomap[PDC_MMIO_BAR]; in pdc20621_dma_prep() local
453 mmio += PDC_CHIP0_OFS; in pdc20621_dma_prep()
483 /* copy three S/G tables and two packets to DIMM MMIO window */ in pdc20621_dma_prep()
491 writel(0x00000001, mmio + PDC_20621_GENERAL_CTL); in pdc20621_dma_prep()
493 readl(dimm_mmio); /* MMIO PCI posting flush */ in pdc20621_dma_prep()
495 VPRINTK("ata pkt buf ofs %u, prd size %u, mmio copied\n", i, sgt_len); in pdc20621_dma_prep()
502 void __iomem *mmio = ap->host->iomap[PDC_MMIO_BAR]; in pdc20621_nodata_prep() local
510 mmio += PDC_CHIP0_OFS; in pdc20621_nodata_prep()
521 /* copy three S/G tables and two packets to DIMM MMIO window */ in pdc20621_nodata_prep()
526 writel(0x00000001, mmio + PDC_20621_GENERAL_CTL); in pdc20621_nodata_prep()
[all …]
H A Dahci_imx.c117 static int imx_phy_crbit_assert(void __iomem *mmio, u32 bit, bool assert) in imx_phy_crbit_assert() argument
124 crval = readl(mmio + IMX_P0PHYCR); in imx_phy_crbit_assert()
129 writel(crval, mmio + IMX_P0PHYCR); in imx_phy_crbit_assert()
133 srval = readl(mmio + IMX_P0PHYSR); in imx_phy_crbit_assert()
142 static int imx_phy_reg_addressing(u16 addr, void __iomem *mmio) in imx_phy_reg_addressing() argument
148 writel(crval, mmio + IMX_P0PHYCR); in imx_phy_reg_addressing()
151 ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_CAP_ADDR, true); in imx_phy_reg_addressing()
156 ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_CAP_ADDR, false); in imx_phy_reg_addressing()
163 static int imx_phy_reg_write(u16 val, void __iomem *mmio) in imx_phy_reg_write() argument
169 writel(crval, mmio + IMX_P0PHYCR); in imx_phy_reg_write()
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/i915/gvt/
H A Dmmio_context.c200 struct engine_mmio *mmio; in restore_context_mmio_for_inhibit() local
217 for (mmio = gvt->engine_mmio_list.mmio; in restore_context_mmio_for_inhibit()
218 i915_mmio_reg_valid(mmio->reg); mmio++) { in restore_context_mmio_for_inhibit()
219 if (mmio->id != ring_id || !mmio->in_context) in restore_context_mmio_for_inhibit()
222 *cs++ = i915_mmio_reg_offset(mmio->reg); in restore_context_mmio_for_inhibit()
223 *cs++ = vgpu_vreg_t(vgpu, mmio->reg) | (mmio->mask << 16); in restore_context_mmio_for_inhibit()
293 * Use lri command to initialize the mmio which is in context state image for
294 * inhibit context, it contains tracked engine mmio, render_mocs and
466 /* Switch ring mmio values (context). */
473 struct engine_mmio *mmio; in switch_mmio() local
[all …]
/OK3568_Linux_fs/u-boot/drivers/phy/
H A Dphy-rockchip-naneng-combphy.c76 void __iomem *mmio; member
288 priv->mmio = (void __iomem *)dev_read_addr(udev); in rockchip_combphy_probe()
289 if (IS_ERR(priv->mmio)) in rockchip_combphy_probe()
290 return PTR_ERR(priv->mmio); in rockchip_combphy_probe()
313 val = readl(priv->mmio + 0x18); in rk3528_combphy_cfg()
316 writel(val, priv->mmio + 0x18); in rk3528_combphy_cfg()
325 val = readl(priv->mmio + 0x18); in rk3528_combphy_cfg()
328 writel(val, priv->mmio + 0x18); in rk3528_combphy_cfg()
331 val = readl(priv->mmio + 0x200); in rk3528_combphy_cfg()
334 writel(val, priv->mmio + 0x200); in rk3528_combphy_cfg()
[all …]
/OK3568_Linux_fs/kernel/sound/soc/xilinx/
H A Dxlnx_formatter_pcm.c79 void __iomem *mmio; member
92 * @mmio: base address offset
99 void __iomem *mmio; member
287 reg = adata->mmio + XLNX_MM2S_OFFSET + XLNX_AUD_STS; in xlnx_mm2s_irq_handler()
306 reg = adata->mmio + XLNX_S2MM_OFFSET + XLNX_AUD_STS; in xlnx_s2mm_irq_handler()
354 stream_data->mmio = adata->mmio + XLNX_MM2S_OFFSET; in xlnx_formatter_pcm_open()
363 stream_data->mmio = adata->mmio + XLNX_S2MM_OFFSET; in xlnx_formatter_pcm_open()
367 val = readl(adata->mmio + XLNX_AUD_CORE_CONFIG); in xlnx_formatter_pcm_open()
412 val = readl(stream_data->mmio + XLNX_AUD_CTRL); in xlnx_formatter_pcm_open()
414 writel(val, stream_data->mmio + XLNX_AUD_CTRL); in xlnx_formatter_pcm_open()
[all …]
/OK3568_Linux_fs/kernel/drivers/phy/qualcomm/
H A Dphy-qcom-ipq806x-sata.c19 void __iomem *mmio; member
59 reg = readl_relaxed(phy->mmio + SATA_PHY_P0_PARAM3); in qcom_ipq806x_sata_phy_init()
61 writel_relaxed(reg, phy->mmio + SATA_PHY_P0_PARAM3); in qcom_ipq806x_sata_phy_init()
63 reg = readl_relaxed(phy->mmio + SATA_PHY_P0_PARAM0) & in qcom_ipq806x_sata_phy_init()
68 writel_relaxed(reg, phy->mmio + SATA_PHY_P0_PARAM0); in qcom_ipq806x_sata_phy_init()
70 reg = readl_relaxed(phy->mmio + SATA_PHY_P0_PARAM1) & in qcom_ipq806x_sata_phy_init()
77 writel_relaxed(reg, phy->mmio + SATA_PHY_P0_PARAM1); in qcom_ipq806x_sata_phy_init()
79 reg = readl_relaxed(phy->mmio + SATA_PHY_P0_PARAM2) & in qcom_ipq806x_sata_phy_init()
82 writel_relaxed(reg, phy->mmio + SATA_PHY_P0_PARAM2); in qcom_ipq806x_sata_phy_init()
85 reg = readl_relaxed(phy->mmio + SATA_PHY_P0_PARAM4); in qcom_ipq806x_sata_phy_init()
[all …]
/OK3568_Linux_fs/kernel/sound/soc/au1x/
H A Dpsc.h13 void __iomem *mmio; member
26 #define PSC_CTRL(x) ((x)->mmio + PSC_CTRL_OFFSET)
27 #define PSC_SEL(x) ((x)->mmio + PSC_SEL_OFFSET)
28 #define I2S_STAT(x) ((x)->mmio + PSC_I2SSTAT_OFFSET)
29 #define I2S_CFG(x) ((x)->mmio + PSC_I2SCFG_OFFSET)
30 #define I2S_PCR(x) ((x)->mmio + PSC_I2SPCR_OFFSET)
31 #define AC97_CFG(x) ((x)->mmio + PSC_AC97CFG_OFFSET)
32 #define AC97_CDC(x) ((x)->mmio + PSC_AC97CDC_OFFSET)
33 #define AC97_EVNT(x) ((x)->mmio + PSC_AC97EVNT_OFFSET)
34 #define AC97_PCR(x) ((x)->mmio + PSC_AC97PCR_OFFSET)
[all …]
/OK3568_Linux_fs/kernel/drivers/ntb/hw/amd/
H A Dntb_hw_amd.c125 void __iomem *mmio, *peer_mmio; in amd_ntb_mw_set_trans() local
142 mmio = ndev->self_mmio; in amd_ntb_mw_set_trans()
166 write64(base_addr, mmio + limit_reg); in amd_ntb_mw_set_trans()
189 writel(base_addr, mmio + limit_reg); in amd_ntb_mw_set_trans()
346 void __iomem *mmio = ndev->self_mmio; in amd_ntb_link_enable() local
350 writel(ndev->int_mask, mmio + AMD_INTMASK_OFFSET); in amd_ntb_link_enable()
362 void __iomem *mmio = ndev->self_mmio; in amd_ntb_link_disable() local
366 writel(ndev->int_mask, mmio + AMD_INTMASK_OFFSET); in amd_ntb_link_disable()
423 void __iomem *mmio = ndev->self_mmio; in amd_ntb_db_read() local
425 return (u64)readw(mmio + AMD_DBSTAT_OFFSET); in amd_ntb_db_read()
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/hisilicon/hibmc/
H A Dhibmc_drm_de.c120 writel(gpu_addr, priv->mmio + HIBMC_CRT_FB_ADDRESS); in hibmc_plane_atomic_update()
127 priv->mmio + HIBMC_CRT_FB_WIDTH); in hibmc_plane_atomic_update()
130 reg = readl(priv->mmio + HIBMC_CRT_DISP_CTL); in hibmc_plane_atomic_update()
134 writel(reg, priv->mmio + HIBMC_CRT_DISP_CTL); in hibmc_plane_atomic_update()
165 reg = readl(priv->mmio + HIBMC_CRT_DISP_CTL); in hibmc_crtc_dpms()
171 writel(reg, priv->mmio + HIBMC_CRT_DISP_CTL); in hibmc_crtc_dpms()
183 reg = readl(priv->mmio + HIBMC_CURRENT_GATE); in hibmc_crtc_atomic_enable()
205 reg = readl(priv->mmio + HIBMC_CURRENT_GATE); in hibmc_crtc_atomic_disable()
259 val = readl(priv->mmio + CRT_PLL1_HS); in set_vclock_hisilicon()
261 writel(val, priv->mmio + CRT_PLL1_HS); in set_vclock_hisilicon()
[all …]
/OK3568_Linux_fs/kernel/drivers/ntb/hw/intel/
H A Dntb_hw_gen1.c203 void __iomem *mmio) in ndev_db_read() argument
208 return ndev->reg->db_ioread(mmio); in ndev_db_read()
212 void __iomem *mmio) in ndev_db_write() argument
220 ndev->reg->db_iowrite(db_bits, mmio); in ndev_db_write()
226 void __iomem *mmio) in ndev_db_set_mask() argument
239 ndev->reg->db_iowrite(ndev->db_mask, mmio); in ndev_db_set_mask()
247 void __iomem *mmio) in ndev_db_clear_mask() argument
260 ndev->reg->db_iowrite(ndev->db_mask, mmio); in ndev_db_clear_mask()
297 void __iomem *mmio) in ndev_spad_read() argument
305 return ioread32(mmio + (idx << 2)); in ndev_spad_read()
[all …]
H A Dntb_hw_gen3.c147 void __iomem *mmio; in gen3_setup_b2b_mw() local
151 mmio = ndev->self_mmio; in gen3_setup_b2b_mw()
155 iowrite64(bar_addr, mmio + GEN3_IMBAR1XLMT_OFFSET); in gen3_setup_b2b_mw()
156 bar_addr = ioread64(mmio + GEN3_IMBAR1XLMT_OFFSET); in gen3_setup_b2b_mw()
160 iowrite64(bar_addr, mmio + GEN3_IMBAR2XLMT_OFFSET); in gen3_setup_b2b_mw()
161 bar_addr = ioread64(mmio + GEN3_IMBAR2XLMT_OFFSET); in gen3_setup_b2b_mw()
165 iowrite64(0, mmio + GEN3_IMBAR1XBASE_OFFSET); in gen3_setup_b2b_mw()
166 iowrite64(0, mmio + GEN3_IMBAR2XBASE_OFFSET); in gen3_setup_b2b_mw()
259 void __iomem *mmio; in ndev_ntb3_debugfs_read() local
266 mmio = ndev->self_mmio; in ndev_ntb3_debugfs_read()
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/OK3568_Linux_fs/kernel/drivers/watchdog/
H A Dvia_wdt.c25 #define VIA_WDT_MMIO_BASE 0xe8 /* MMIO region base address */
30 #define VIA_WDT_CONF_MMIO 0x02 /* 1: enable watchdog MMIO */
33 * The MMIO region contains the watchdog control register and the
36 #define VIA_WDT_MMIO_LEN 8 /* MMIO region length in bytes */
37 #define VIA_WDT_CTL 0 /* MMIO addr+0: state/control reg. */
38 #define VIA_WDT_COUNT 4 /* MMIO addr+4: timer counter reg. */
69 static unsigned int mmio; variable
170 * Allocate a MMIO region which contains watchdog control register in wdt_probe()
177 dev_err(&pdev->dev, "MMIO allocation failed\n"); in wdt_probe()
186 pci_read_config_dword(pdev, VIA_WDT_MMIO_BASE, &mmio); in wdt_probe()
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