| /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/clock/ |
| H A D | mvebu-gated-clock.txt | 7 corresponding clock gating control bit in HW to ease manual clock
177 "marvell,armada-370-gating-clock" - for Armada 370 SoC clock gating
178 "marvell,armada-375-gating-clock" - for Armada 375 SoC clock gating
179 "marvell,armada-380-gating-clock" - for Armada 380/385 SoC clock gating
180 "marvell,armada-390-gating-clock" - for Armada 39x SoC clock gating
181 "marvell,armada-xp-gating-clock" - for Armada XP SoC clock gating
182 "marvell,mv98dx3236-gating-clock" - for 98dx3236 SoC clock gating
183 "marvell,dove-gating-clock" - for Dove SoC clock gating
184 "marvell,kirkwood-gating-clock" - for Kirkwood SoC clock gating
185 - reg : shall be the register address of the Clock Gating Control register
[all …]
|
| H A D | zx296718-clk.txt | 10 zx296718 top clock selection, divider and gating
14 zx296718 device level clock selection and gating
17 zx296718 audio clock selection, divider and gating
|
| H A D | zx296702-clk.txt | 10 zx296702 top clock selection, divider and gating
14 zx296702 device level clock selection and gating
|
| /OK3568_Linux_fs/kernel/sound/soc/intel/catpt/ |
| H A D | dsp.c | 169 /* wait for SRAM power gating to propagate */ in catpt_dsp_set_srampge()
207 /* disable core clock gating */ in catpt_dsp_update_srampge()
212 /* enable core clock gating */ in catpt_dsp_update_srampge()
366 /* DRAM power gating all */ in lpt_dsp_power_down()
381 /* SRAM power gating none */ in lpt_dsp_power_up()
407 /* disable core clock gating */ in wpt_dsp_power_down()
420 /* switch clock gating */ in wpt_dsp_power_down()
428 /* SRAM power gating all */ in wpt_dsp_power_down()
440 /* enable core clock gating */ in wpt_dsp_power_down()
452 /* disable core clock gating */ in wpt_dsp_power_up()
[all …]
|
| /OK3568_Linux_fs/kernel/drivers/clk/qcom/ |
| H A D | clk-branch.h | 12 * struct clk_branch - gating clock with status bit and dynamic hardware gating
14 * @hwcg_reg: dynamic hardware clock gating register
15 * @hwcg_bit: ORed with @hwcg_reg to enable dynamic hardware clock gating
|
| /OK3568_Linux_fs/u-boot/board/gateworks/gw_ventana/ |
| H A D | gw_ventana_spl.c | 214 /* Read DQS Gating calibration */
227 /* Read DQS Gating calibration */
240 /* Read DQS Gating calibration */
253 /* Read DQS Gating calibration */
266 /* Read DQS Gating calibration */
281 /* Read DQS Gating calibration */
300 /* Read DQS Gating calibration */
317 /* Read DQS Gating calibration */
330 /* Read DQS Gating calibration */
345 /* Read DQS Gating calibration */
[all …]
|
| /OK3568_Linux_fs/u-boot/arch/arm/cpu/armv7/bcm235xx/ |
| H A D | clk-core.h | 122 * Gating control and status is managed by a 32-bit gate register.
124 * There are several types of gating available:
127 * - hardware-only gating (auto-gating)
132 * - software-only gating
133 * Auto-gating is not available for this type of clock.
137 * To ensure a change to the gating status is complete, the
140 * - selectable hardware or software gating
141 * Gating for this type of clock can be configured to be either
149 u32 hw_sw_sel_bit; /* 0: hardware gating; 1: software gating */
|
| /OK3568_Linux_fs/u-boot/arch/arm/cpu/armv7/bcm281xx/ |
| H A D | clk-core.h | 122 * Gating control and status is managed by a 32-bit gate register.
124 * There are several types of gating available:
127 * - hardware-only gating (auto-gating)
132 * - software-only gating
133 * Auto-gating is not available for this type of clock.
137 * To ensure a change to the gating status is complete, the
140 * - selectable hardware or software gating
141 * Gating for this type of clock can be configured to be either
149 u32 hw_sw_sel_bit; /* 0: hardware gating; 1: software gating */
|
| /OK3568_Linux_fs/kernel/drivers/gpu/drm/i915/gt/ |
| H A D | intel_sseu.c | 160 /* TGL only supports slice-level power gating */ in gen12_sseu_info_init()
186 /* ICL has no power gating restrictions. */ in gen11_sseu_info_init()
263 /* No restrictions on Power Gating */ in gen10_sseu_info_init()
315 * CHV supports subslice power gating on devices with more than in cherryview_sseu_info_init()
316 * one subslice, and supports EU power gating on devices with in cherryview_sseu_info_init()
401 * SKL+ supports slice power gating on devices with more than in gen9_sseu_info_init()
402 * one slice, and supports EU power gating on devices with in gen9_sseu_info_init()
404 * power gating on devices with more than one subslice, and in gen9_sseu_info_init()
405 * supports EU power gating on devices with more than one EU in gen9_sseu_info_init()
508 * BDW supports slice power gating on devices with more than in bdw_sseu_info_init()
[all …]
|
| /OK3568_Linux_fs/kernel/drivers/staging/gasket/ |
| H A D | apex.h | 12 /* Clock Gating ioctl. */
17 /* If set, enter clock gating state, regardless of custom block's
26 /* Enable/Disable clock gating. */
|
| /OK3568_Linux_fs/kernel/drivers/clk/bcm/ |
| H A D | clk-kona.h | 106 * Gating control and status is managed by a 32-bit gate register.
108 * There are several types of gating available:
111 * - hardware-only gating (auto-gating)
116 * - software-only gating
117 * Auto-gating is not available for this type of clock.
121 * To ensure a change to the gating status is complete, the
124 * - selectable hardware or software gating
125 * Gating for this type of clock can be configured to be either
133 u32 hw_sw_sel_bit; /* 0: hardware gating; 1: software gating */
|
| /OK3568_Linux_fs/kernel/drivers/soc/tegra/ |
| H A D | flowctrl.c | 84 /* pwr gating on wfe */ in flowctrl_cpu_suspend_enter()
99 * power-gating (like memory running off PLLP), in flowctrl_cpu_suspend_enter()
103 * while wfe for the power-gating, just like it in flowctrl_cpu_suspend_enter()
108 /* pwr gating on wfi */ in flowctrl_cpu_suspend_enter()
115 reg |= FLOW_CTRL_CSR_ENABLE; /* pwr gating */ in flowctrl_cpu_suspend_enter()
|
| /OK3568_Linux_fs/u-boot/arch/arm/include/asm/arch-s32v234/ |
| H A D | lpddr2.h | 58 #define MMDC_MPDGCTRL0_MODULE0_VALUE 0x20000000 /* Read DQS gating control 0 (disabled) */
59 #define MMDC_MPDGCTRL1_MODULE0_VALUE 0x00000000 /* Read DQS gating control 1 */
63 #define MMDC_MPDGCTRL0_MODULE1_VALUE 0x20000000 /* Read DQS gating control 0 (disabled) */
64 #define MMDC_MPDGCTRL1_MODULE1_VALUE 0x00000000 /* Read DQS gating control 1 */
|
| /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/dram/ |
| H A D | rk3399_dram_timing.txt | 16 - sr_idle : Defines the Self-Refresh or Self-Refresh with Memory Clock Gating
20 or Self-Refresh with Memory Clock Gating low power state.
22 - sr_mc_gate_idle : Defined the Self-Refresh with Memory and Controller Clock Gating
26 Memory and Controller Clock Gating low power state.
|
| /OK3568_Linux_fs/kernel/arch/arm/mach-ux500/ |
| H A D | pm_domains.c | 21 * Handle the gating of the PM domain regulator here. in pd_power_off()
25 * callbacks, to be able to enable PM domain gating/ungating. in pd_power_off()
37 * callbacks, to be able to enable PM domain gating/ungating. in pd_power_on()
|
| /OK3568_Linux_fs/u-boot/arch/arm/mach-sunxi/ |
| H A D | dram_sun4i.c | 357 * bits [31:26] - DQS gating system latency for byte lane 3
358 * bits [25:24] - DQS gating phase select for byte lane 3
359 * bits [23:18] - DQS gating system latency for byte lane 2
360 * bits [17:16] - DQS gating phase select for byte lane 2
361 * bits [15:10] - DQS gating system latency for byte lane 1
362 * bits [ 9:8 ] - DQS gating phase select for byte lane 1
363 * bits [ 7:2 ] - DQS gating system latency for byte lane 0
364 * bits [ 1:0 ] - DQS gating phase select for byte lane 0
370 /* rank0 gating system latency (3 bits per lane: cycles) */ in mctl_set_dqs_gating_delay()
372 /* rank0 gating phase select (2 bits per lane: 90, 180, 270, 360) */ in mctl_set_dqs_gating_delay()
[all …]
|
| /OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/pm/inc/ |
| H A D | hardwaremanager.h | 95 …PHM_PlatformCaps_DisableMGClockGating, /* to disable Medium Grain Clock Gating or…
96 …PHM_PlatformCaps_DisableMGCGTSSM, /* TO disable Medium Grain Clock Gating Sh…
98 PHM_PlatformCaps_DisablePowerGating, /* to disable power gating */
148 …PHM_PlatformCaps_UVDPowerGating, /* enable UVD power gating, supported from…
149 …PHM_PlatformCaps_UVDDynamicPowerGating, /* enable UVD Dynamic power gating, suppor…
150 …PHM_PlatformCaps_VCEPowerGating, /* Enable VCE power gating, supported for …
151 …PHM_PlatformCaps_SamuPowerGating, /* Enable SAMU power gating, supported for…
|
| /OK3568_Linux_fs/kernel/sound/pci/hda/ |
| H A D | hda_jack.c | 196 /* A gating jack indicates the jack is invalid if gating is unplugged */ in jack_detect_update()
365 * snd_hda_jack_set_gating_jack - Set gating jack.
368 * @gating_nid: gating pin NID
370 * Indicates the gated jack is only valid when the gating jack is plugged.
376 struct hda_jack_tbl *gating = in snd_hda_jack_set_gating_jack() local
381 if (!gated || !gating) in snd_hda_jack_set_gating_jack()
385 gating->gated_jack = gated_nid; in snd_hda_jack_set_gating_jack()
407 * to make sure that all gating jacks properly have been set in snd_hda_jack_report_sync()
|
| /OK3568_Linux_fs/kernel/drivers/gpu/drm/gma500/ |
| H A D | psb_device.c | 154 u32 gating = PSB_RSGX32(PSB_CR_CLKGATECTL); in psb_init_pm() local
155 gating &= ~3; /* Disable 2D clock gating */ in psb_init_pm()
156 gating |= 1; in psb_init_pm()
157 PSB_WSGX32(gating, PSB_CR_CLKGATECTL); in psb_init_pm()
|
| /OK3568_Linux_fs/u-boot/arch/arm/include/asm/arch-sunxi/ |
| H A D | clock_sun9i.h | 84 u32 ahb_gate0; /* 0x580 AHB0 Gating Register */
85 u32 ahb_gate1; /* 0x584 AHB1 Gating Register */
86 u32 ahb_gate2; /* 0x588 AHB2 Gating Register */
88 u32 apb0_gate; /* 0x590 APB0 Clock Gating Register */
89 u32 apb1_gate; /* 0x594 APB1 Clock Gating Register */
|
| H A D | clock_sun8i_a83t.h | 38 u32 ahb_gate0; /* 0x60 ahb module clock gating 0 */
39 u32 ahb_gate1; /* 0x64 ahb module clock gating 1 */
40 u32 apb1_gate; /* 0x68 apb1 module clock gating 3 */
41 u32 apb2_gate; /* 0x6c apb2 module clock gating 4 */
67 u32 dram_clk_gate; /* 0x100 DRAM module gating */
|
| H A D | clock_sun6i.h | 38 u32 axi_gate; /* 0x5c axi module clock gating */
39 u32 ahb_gate0; /* 0x60 ahb module clock gating 0 */
40 u32 ahb_gate1; /* 0x64 ahb module clock gating 1 */
41 u32 apb1_gate; /* 0x68 apb1 module clock gating */
42 u32 apb2_gate; /* 0x6c apb2 module clock gating */
43 u32 bus_gate4; /* 0x70 gate 4 module clock gating */
70 u32 dram_clk_gate; /* 0x100 DRAM module gating */
|
| /OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/amdgpu/ |
| H A D | vcn_v3_0.c | 645 * vcn_v3_0_disable_clock_gating - disable VCN clock gating
650 * Disable clock gating for VCN block
785 /* enable sw clock gating control */ in vcn_v3_0_clock_gating_dpg_mode()
815 /* turn off clock gating */ in vcn_v3_0_clock_gating_dpg_mode()
819 /* turn on SUVD clock gating */ in vcn_v3_0_clock_gating_dpg_mode()
829 * vcn_v3_0_enable_clock_gating - enable VCN clock gating
834 * Enable clock gating for VCN block
904 /* enable dynamic power gating mode */ in vcn_v3_0_start_dpg_mode()
913 /* enable clock gating */ in vcn_v3_0_start_dpg_mode()
1059 /* disable VCN power gating */ in vcn_v3_0_start()
[all …]
|
| H A D | vcn_v1_0.c | 442 * vcn_v1_0_disable_clock_gating - disable VCN clock gating
445 * @sw: enable SW clock gating
447 * Disable clock gating for VCN block
569 * vcn_v1_0_enable_clock_gating - enable VCN clock gating
572 * @sw: enable SW clock gating
574 * Enable clock gating for VCN block
656 /* enable sw clock gating control */ in vcn_v1_0_clock_gating_dpg_mode()
685 /* turn off clock gating */ in vcn_v1_0_clock_gating_dpg_mode()
688 /* turn on SUVD clock gating */ in vcn_v1_0_clock_gating_dpg_mode()
803 /* disable clock gating */ in vcn_v1_0_start_spg_mode()
[all …]
|
| /OK3568_Linux_fs/kernel/drivers/misc/mei/ |
| H A D | mei_dev.h | 285 * @pg_state : power gating state of the device
287 * @pg_is_enabled : is power gating enabled
354 * enum mei_pg_event - power gating transition events
356 * @MEI_PG_EVENT_IDLE: the driver is not in power gating transition
371 * enum mei_pg_state - device internal power gating state
432 * @pg_event : power gating event
513 * Power Gating support
|