xref: /OK3568_Linux_fs/kernel/drivers/misc/mei/mei_dev.h (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * Copyright (c) 2003-2019, Intel Corporation. All rights reserved.
4*4882a593Smuzhiyun  * Intel Management Engine Interface (Intel MEI) Linux driver
5*4882a593Smuzhiyun  */
6*4882a593Smuzhiyun 
7*4882a593Smuzhiyun #ifndef _MEI_DEV_H_
8*4882a593Smuzhiyun #define _MEI_DEV_H_
9*4882a593Smuzhiyun 
10*4882a593Smuzhiyun #include <linux/types.h>
11*4882a593Smuzhiyun #include <linux/cdev.h>
12*4882a593Smuzhiyun #include <linux/poll.h>
13*4882a593Smuzhiyun #include <linux/mei.h>
14*4882a593Smuzhiyun #include <linux/mei_cl_bus.h>
15*4882a593Smuzhiyun 
16*4882a593Smuzhiyun #include "hw.h"
17*4882a593Smuzhiyun #include "hbm.h"
18*4882a593Smuzhiyun 
19*4882a593Smuzhiyun #define MEI_SLOT_SIZE             sizeof(u32)
20*4882a593Smuzhiyun #define MEI_RD_MSG_BUF_SIZE       (128 * MEI_SLOT_SIZE)
21*4882a593Smuzhiyun 
22*4882a593Smuzhiyun /*
23*4882a593Smuzhiyun  * Number of Maximum MEI Clients
24*4882a593Smuzhiyun  */
25*4882a593Smuzhiyun #define MEI_CLIENTS_MAX 256
26*4882a593Smuzhiyun 
27*4882a593Smuzhiyun /*
28*4882a593Smuzhiyun  * maximum number of consecutive resets
29*4882a593Smuzhiyun  */
30*4882a593Smuzhiyun #define MEI_MAX_CONSEC_RESET  3
31*4882a593Smuzhiyun 
32*4882a593Smuzhiyun /*
33*4882a593Smuzhiyun  * Number of File descriptors/handles
34*4882a593Smuzhiyun  * that can be opened to the driver.
35*4882a593Smuzhiyun  *
36*4882a593Smuzhiyun  * Limit to 255: 256 Total Clients
37*4882a593Smuzhiyun  * minus internal client for MEI Bus Messages
38*4882a593Smuzhiyun  */
39*4882a593Smuzhiyun #define  MEI_MAX_OPEN_HANDLE_COUNT (MEI_CLIENTS_MAX - 1)
40*4882a593Smuzhiyun 
41*4882a593Smuzhiyun /* File state */
42*4882a593Smuzhiyun enum file_state {
43*4882a593Smuzhiyun 	MEI_FILE_UNINITIALIZED = 0,
44*4882a593Smuzhiyun 	MEI_FILE_INITIALIZING,
45*4882a593Smuzhiyun 	MEI_FILE_CONNECTING,
46*4882a593Smuzhiyun 	MEI_FILE_CONNECTED,
47*4882a593Smuzhiyun 	MEI_FILE_DISCONNECTING,
48*4882a593Smuzhiyun 	MEI_FILE_DISCONNECT_REPLY,
49*4882a593Smuzhiyun 	MEI_FILE_DISCONNECT_REQUIRED,
50*4882a593Smuzhiyun 	MEI_FILE_DISCONNECTED,
51*4882a593Smuzhiyun };
52*4882a593Smuzhiyun 
53*4882a593Smuzhiyun /* MEI device states */
54*4882a593Smuzhiyun enum mei_dev_state {
55*4882a593Smuzhiyun 	MEI_DEV_INITIALIZING = 0,
56*4882a593Smuzhiyun 	MEI_DEV_INIT_CLIENTS,
57*4882a593Smuzhiyun 	MEI_DEV_ENABLED,
58*4882a593Smuzhiyun 	MEI_DEV_RESETTING,
59*4882a593Smuzhiyun 	MEI_DEV_DISABLED,
60*4882a593Smuzhiyun 	MEI_DEV_POWER_DOWN,
61*4882a593Smuzhiyun 	MEI_DEV_POWER_UP
62*4882a593Smuzhiyun };
63*4882a593Smuzhiyun 
64*4882a593Smuzhiyun const char *mei_dev_state_str(int state);
65*4882a593Smuzhiyun 
66*4882a593Smuzhiyun enum mei_file_transaction_states {
67*4882a593Smuzhiyun 	MEI_IDLE,
68*4882a593Smuzhiyun 	MEI_WRITING,
69*4882a593Smuzhiyun 	MEI_WRITE_COMPLETE,
70*4882a593Smuzhiyun };
71*4882a593Smuzhiyun 
72*4882a593Smuzhiyun /**
73*4882a593Smuzhiyun  * enum mei_cb_file_ops  - file operation associated with the callback
74*4882a593Smuzhiyun  * @MEI_FOP_READ:       read
75*4882a593Smuzhiyun  * @MEI_FOP_WRITE:      write
76*4882a593Smuzhiyun  * @MEI_FOP_CONNECT:    connect
77*4882a593Smuzhiyun  * @MEI_FOP_DISCONNECT: disconnect
78*4882a593Smuzhiyun  * @MEI_FOP_DISCONNECT_RSP: disconnect response
79*4882a593Smuzhiyun  * @MEI_FOP_NOTIFY_START:   start notification
80*4882a593Smuzhiyun  * @MEI_FOP_NOTIFY_STOP:    stop notification
81*4882a593Smuzhiyun  */
82*4882a593Smuzhiyun enum mei_cb_file_ops {
83*4882a593Smuzhiyun 	MEI_FOP_READ = 0,
84*4882a593Smuzhiyun 	MEI_FOP_WRITE,
85*4882a593Smuzhiyun 	MEI_FOP_CONNECT,
86*4882a593Smuzhiyun 	MEI_FOP_DISCONNECT,
87*4882a593Smuzhiyun 	MEI_FOP_DISCONNECT_RSP,
88*4882a593Smuzhiyun 	MEI_FOP_NOTIFY_START,
89*4882a593Smuzhiyun 	MEI_FOP_NOTIFY_STOP,
90*4882a593Smuzhiyun };
91*4882a593Smuzhiyun 
92*4882a593Smuzhiyun /**
93*4882a593Smuzhiyun  * enum mei_cl_io_mode - io mode between driver and fw
94*4882a593Smuzhiyun  *
95*4882a593Smuzhiyun  * @MEI_CL_IO_TX_BLOCKING: send is blocking
96*4882a593Smuzhiyun  * @MEI_CL_IO_TX_INTERNAL: internal communication between driver and FW
97*4882a593Smuzhiyun  *
98*4882a593Smuzhiyun  * @MEI_CL_IO_RX_NONBLOCK: recv is non-blocking
99*4882a593Smuzhiyun  */
100*4882a593Smuzhiyun enum mei_cl_io_mode {
101*4882a593Smuzhiyun 	MEI_CL_IO_TX_BLOCKING = BIT(0),
102*4882a593Smuzhiyun 	MEI_CL_IO_TX_INTERNAL = BIT(1),
103*4882a593Smuzhiyun 
104*4882a593Smuzhiyun 	MEI_CL_IO_RX_NONBLOCK = BIT(2),
105*4882a593Smuzhiyun };
106*4882a593Smuzhiyun 
107*4882a593Smuzhiyun /*
108*4882a593Smuzhiyun  * Intel MEI message data struct
109*4882a593Smuzhiyun  */
110*4882a593Smuzhiyun struct mei_msg_data {
111*4882a593Smuzhiyun 	size_t size;
112*4882a593Smuzhiyun 	unsigned char *data;
113*4882a593Smuzhiyun };
114*4882a593Smuzhiyun 
115*4882a593Smuzhiyun /**
116*4882a593Smuzhiyun  * struct mei_dma_dscr - dma address descriptor
117*4882a593Smuzhiyun  *
118*4882a593Smuzhiyun  * @vaddr: dma buffer virtual address
119*4882a593Smuzhiyun  * @daddr: dma buffer physical address
120*4882a593Smuzhiyun  * @size : dma buffer size
121*4882a593Smuzhiyun  */
122*4882a593Smuzhiyun struct mei_dma_dscr {
123*4882a593Smuzhiyun 	void *vaddr;
124*4882a593Smuzhiyun 	dma_addr_t daddr;
125*4882a593Smuzhiyun 	size_t size;
126*4882a593Smuzhiyun };
127*4882a593Smuzhiyun 
128*4882a593Smuzhiyun /* Maximum number of processed FW status registers */
129*4882a593Smuzhiyun #define MEI_FW_STATUS_MAX 6
130*4882a593Smuzhiyun /* Minimal  buffer for FW status string (8 bytes in dw + space or '\0') */
131*4882a593Smuzhiyun #define MEI_FW_STATUS_STR_SZ (MEI_FW_STATUS_MAX * (8 + 1))
132*4882a593Smuzhiyun 
133*4882a593Smuzhiyun 
134*4882a593Smuzhiyun /*
135*4882a593Smuzhiyun  * struct mei_fw_status - storage of FW status data
136*4882a593Smuzhiyun  *
137*4882a593Smuzhiyun  * @count: number of actually available elements in array
138*4882a593Smuzhiyun  * @status: FW status registers
139*4882a593Smuzhiyun  */
140*4882a593Smuzhiyun struct mei_fw_status {
141*4882a593Smuzhiyun 	int count;
142*4882a593Smuzhiyun 	u32 status[MEI_FW_STATUS_MAX];
143*4882a593Smuzhiyun };
144*4882a593Smuzhiyun 
145*4882a593Smuzhiyun /**
146*4882a593Smuzhiyun  * struct mei_me_client - representation of me (fw) client
147*4882a593Smuzhiyun  *
148*4882a593Smuzhiyun  * @list: link in me client list
149*4882a593Smuzhiyun  * @refcnt: struct reference count
150*4882a593Smuzhiyun  * @props: client properties
151*4882a593Smuzhiyun  * @client_id: me client id
152*4882a593Smuzhiyun  * @tx_flow_ctrl_creds: flow control credits
153*4882a593Smuzhiyun  * @connect_count: number connections to this client
154*4882a593Smuzhiyun  * @bus_added: added to bus
155*4882a593Smuzhiyun  */
156*4882a593Smuzhiyun struct mei_me_client {
157*4882a593Smuzhiyun 	struct list_head list;
158*4882a593Smuzhiyun 	struct kref refcnt;
159*4882a593Smuzhiyun 	struct mei_client_properties props;
160*4882a593Smuzhiyun 	u8 client_id;
161*4882a593Smuzhiyun 	u8 tx_flow_ctrl_creds;
162*4882a593Smuzhiyun 	u8 connect_count;
163*4882a593Smuzhiyun 	u8 bus_added;
164*4882a593Smuzhiyun };
165*4882a593Smuzhiyun 
166*4882a593Smuzhiyun 
167*4882a593Smuzhiyun struct mei_cl;
168*4882a593Smuzhiyun 
169*4882a593Smuzhiyun /**
170*4882a593Smuzhiyun  * struct mei_cl_cb - file operation callback structure
171*4882a593Smuzhiyun  *
172*4882a593Smuzhiyun  * @list: link in callback queue
173*4882a593Smuzhiyun  * @cl: file client who is running this operation
174*4882a593Smuzhiyun  * @fop_type: file operation type
175*4882a593Smuzhiyun  * @buf: buffer for data associated with the callback
176*4882a593Smuzhiyun  * @buf_idx: last read index
177*4882a593Smuzhiyun  * @vtag: virtual tag
178*4882a593Smuzhiyun  * @fp: pointer to file structure
179*4882a593Smuzhiyun  * @status: io status of the cb
180*4882a593Smuzhiyun  * @internal: communication between driver and FW flag
181*4882a593Smuzhiyun  * @blocking: transmission blocking mode
182*4882a593Smuzhiyun  */
183*4882a593Smuzhiyun struct mei_cl_cb {
184*4882a593Smuzhiyun 	struct list_head list;
185*4882a593Smuzhiyun 	struct mei_cl *cl;
186*4882a593Smuzhiyun 	enum mei_cb_file_ops fop_type;
187*4882a593Smuzhiyun 	struct mei_msg_data buf;
188*4882a593Smuzhiyun 	size_t buf_idx;
189*4882a593Smuzhiyun 	u8 vtag;
190*4882a593Smuzhiyun 	const struct file *fp;
191*4882a593Smuzhiyun 	int status;
192*4882a593Smuzhiyun 	u32 internal:1;
193*4882a593Smuzhiyun 	u32 blocking:1;
194*4882a593Smuzhiyun };
195*4882a593Smuzhiyun 
196*4882a593Smuzhiyun /**
197*4882a593Smuzhiyun  * struct mei_cl_vtag - file pointer to vtag mapping structure
198*4882a593Smuzhiyun  *
199*4882a593Smuzhiyun  * @list: link in map queue
200*4882a593Smuzhiyun  * @fp: file pointer
201*4882a593Smuzhiyun  * @vtag: corresponding vtag
202*4882a593Smuzhiyun  * @pending_read: the read is pending on this file
203*4882a593Smuzhiyun  */
204*4882a593Smuzhiyun struct mei_cl_vtag {
205*4882a593Smuzhiyun 	struct list_head list;
206*4882a593Smuzhiyun 	const struct file *fp;
207*4882a593Smuzhiyun 	u8 vtag;
208*4882a593Smuzhiyun 	u8 pending_read:1;
209*4882a593Smuzhiyun };
210*4882a593Smuzhiyun 
211*4882a593Smuzhiyun /**
212*4882a593Smuzhiyun  * struct mei_cl - me client host representation
213*4882a593Smuzhiyun  *    carried in file->private_data
214*4882a593Smuzhiyun  *
215*4882a593Smuzhiyun  * @link: link in the clients list
216*4882a593Smuzhiyun  * @dev: mei parent device
217*4882a593Smuzhiyun  * @state: file operation state
218*4882a593Smuzhiyun  * @tx_wait: wait queue for tx completion
219*4882a593Smuzhiyun  * @rx_wait: wait queue for rx completion
220*4882a593Smuzhiyun  * @wait:  wait queue for management operation
221*4882a593Smuzhiyun  * @ev_wait: notification wait queue
222*4882a593Smuzhiyun  * @ev_async: event async notification
223*4882a593Smuzhiyun  * @status: connection status
224*4882a593Smuzhiyun  * @me_cl: fw client connected
225*4882a593Smuzhiyun  * @fp: file associated with client
226*4882a593Smuzhiyun  * @host_client_id: host id
227*4882a593Smuzhiyun  * @vtag_map: vtag map
228*4882a593Smuzhiyun  * @tx_flow_ctrl_creds: transmit flow credentials
229*4882a593Smuzhiyun  * @rx_flow_ctrl_creds: receive flow credentials
230*4882a593Smuzhiyun  * @timer_count:  watchdog timer for operation completion
231*4882a593Smuzhiyun  * @notify_en: notification - enabled/disabled
232*4882a593Smuzhiyun  * @notify_ev: pending notification event
233*4882a593Smuzhiyun  * @tx_cb_queued: number of tx callbacks in queue
234*4882a593Smuzhiyun  * @writing_state: state of the tx
235*4882a593Smuzhiyun  * @rd_pending: pending read credits
236*4882a593Smuzhiyun  * @rd_completed_lock: protects rd_completed queue
237*4882a593Smuzhiyun  * @rd_completed: completed read
238*4882a593Smuzhiyun  *
239*4882a593Smuzhiyun  * @cldev: device on the mei client bus
240*4882a593Smuzhiyun  */
241*4882a593Smuzhiyun struct mei_cl {
242*4882a593Smuzhiyun 	struct list_head link;
243*4882a593Smuzhiyun 	struct mei_device *dev;
244*4882a593Smuzhiyun 	enum file_state state;
245*4882a593Smuzhiyun 	wait_queue_head_t tx_wait;
246*4882a593Smuzhiyun 	wait_queue_head_t rx_wait;
247*4882a593Smuzhiyun 	wait_queue_head_t wait;
248*4882a593Smuzhiyun 	wait_queue_head_t ev_wait;
249*4882a593Smuzhiyun 	struct fasync_struct *ev_async;
250*4882a593Smuzhiyun 	int status;
251*4882a593Smuzhiyun 	struct mei_me_client *me_cl;
252*4882a593Smuzhiyun 	const struct file *fp;
253*4882a593Smuzhiyun 	u8 host_client_id;
254*4882a593Smuzhiyun 	struct list_head vtag_map;
255*4882a593Smuzhiyun 	u8 tx_flow_ctrl_creds;
256*4882a593Smuzhiyun 	u8 rx_flow_ctrl_creds;
257*4882a593Smuzhiyun 	u8 timer_count;
258*4882a593Smuzhiyun 	u8 notify_en;
259*4882a593Smuzhiyun 	u8 notify_ev;
260*4882a593Smuzhiyun 	u8 tx_cb_queued;
261*4882a593Smuzhiyun 	enum mei_file_transaction_states writing_state;
262*4882a593Smuzhiyun 	struct list_head rd_pending;
263*4882a593Smuzhiyun 	spinlock_t rd_completed_lock; /* protects rd_completed queue */
264*4882a593Smuzhiyun 	struct list_head rd_completed;
265*4882a593Smuzhiyun 
266*4882a593Smuzhiyun 	struct mei_cl_device *cldev;
267*4882a593Smuzhiyun };
268*4882a593Smuzhiyun 
269*4882a593Smuzhiyun #define MEI_TX_QUEUE_LIMIT_DEFAULT 50
270*4882a593Smuzhiyun #define MEI_TX_QUEUE_LIMIT_MAX 255
271*4882a593Smuzhiyun #define MEI_TX_QUEUE_LIMIT_MIN 30
272*4882a593Smuzhiyun 
273*4882a593Smuzhiyun /**
274*4882a593Smuzhiyun  * struct mei_hw_ops - hw specific ops
275*4882a593Smuzhiyun  *
276*4882a593Smuzhiyun  * @host_is_ready    : query for host readiness
277*4882a593Smuzhiyun  *
278*4882a593Smuzhiyun  * @hw_is_ready      : query if hw is ready
279*4882a593Smuzhiyun  * @hw_reset         : reset hw
280*4882a593Smuzhiyun  * @hw_start         : start hw after reset
281*4882a593Smuzhiyun  * @hw_config        : configure hw
282*4882a593Smuzhiyun  *
283*4882a593Smuzhiyun  * @fw_status        : get fw status registers
284*4882a593Smuzhiyun  * @trc_status       : get trc status register
285*4882a593Smuzhiyun  * @pg_state         : power gating state of the device
286*4882a593Smuzhiyun  * @pg_in_transition : is device now in pg transition
287*4882a593Smuzhiyun  * @pg_is_enabled    : is power gating enabled
288*4882a593Smuzhiyun  *
289*4882a593Smuzhiyun  * @intr_clear       : clear pending interrupts
290*4882a593Smuzhiyun  * @intr_enable      : enable interrupts
291*4882a593Smuzhiyun  * @intr_disable     : disable interrupts
292*4882a593Smuzhiyun  * @synchronize_irq  : synchronize irqs
293*4882a593Smuzhiyun  *
294*4882a593Smuzhiyun  * @hbuf_free_slots  : query for write buffer empty slots
295*4882a593Smuzhiyun  * @hbuf_is_ready    : query if write buffer is empty
296*4882a593Smuzhiyun  * @hbuf_depth       : query for write buffer depth
297*4882a593Smuzhiyun  *
298*4882a593Smuzhiyun  * @write            : write a message to FW
299*4882a593Smuzhiyun  *
300*4882a593Smuzhiyun  * @rdbuf_full_slots : query how many slots are filled
301*4882a593Smuzhiyun  *
302*4882a593Smuzhiyun  * @read_hdr         : get first 4 bytes (header)
303*4882a593Smuzhiyun  * @read             : read a buffer from the FW
304*4882a593Smuzhiyun  */
305*4882a593Smuzhiyun struct mei_hw_ops {
306*4882a593Smuzhiyun 
307*4882a593Smuzhiyun 	bool (*host_is_ready)(struct mei_device *dev);
308*4882a593Smuzhiyun 
309*4882a593Smuzhiyun 	bool (*hw_is_ready)(struct mei_device *dev);
310*4882a593Smuzhiyun 	int (*hw_reset)(struct mei_device *dev, bool enable);
311*4882a593Smuzhiyun 	int (*hw_start)(struct mei_device *dev);
312*4882a593Smuzhiyun 	int (*hw_config)(struct mei_device *dev);
313*4882a593Smuzhiyun 
314*4882a593Smuzhiyun 	int (*fw_status)(struct mei_device *dev, struct mei_fw_status *fw_sts);
315*4882a593Smuzhiyun 	int (*trc_status)(struct mei_device *dev, u32 *trc);
316*4882a593Smuzhiyun 
317*4882a593Smuzhiyun 	enum mei_pg_state (*pg_state)(struct mei_device *dev);
318*4882a593Smuzhiyun 	bool (*pg_in_transition)(struct mei_device *dev);
319*4882a593Smuzhiyun 	bool (*pg_is_enabled)(struct mei_device *dev);
320*4882a593Smuzhiyun 
321*4882a593Smuzhiyun 	void (*intr_clear)(struct mei_device *dev);
322*4882a593Smuzhiyun 	void (*intr_enable)(struct mei_device *dev);
323*4882a593Smuzhiyun 	void (*intr_disable)(struct mei_device *dev);
324*4882a593Smuzhiyun 	void (*synchronize_irq)(struct mei_device *dev);
325*4882a593Smuzhiyun 
326*4882a593Smuzhiyun 	int (*hbuf_free_slots)(struct mei_device *dev);
327*4882a593Smuzhiyun 	bool (*hbuf_is_ready)(struct mei_device *dev);
328*4882a593Smuzhiyun 	u32 (*hbuf_depth)(const struct mei_device *dev);
329*4882a593Smuzhiyun 	int (*write)(struct mei_device *dev,
330*4882a593Smuzhiyun 		     const void *hdr, size_t hdr_len,
331*4882a593Smuzhiyun 		     const void *data, size_t data_len);
332*4882a593Smuzhiyun 
333*4882a593Smuzhiyun 	int (*rdbuf_full_slots)(struct mei_device *dev);
334*4882a593Smuzhiyun 
335*4882a593Smuzhiyun 	u32 (*read_hdr)(const struct mei_device *dev);
336*4882a593Smuzhiyun 	int (*read)(struct mei_device *dev,
337*4882a593Smuzhiyun 		     unsigned char *buf, unsigned long len);
338*4882a593Smuzhiyun };
339*4882a593Smuzhiyun 
340*4882a593Smuzhiyun /* MEI bus API*/
341*4882a593Smuzhiyun void mei_cl_bus_rescan_work(struct work_struct *work);
342*4882a593Smuzhiyun void mei_cl_bus_dev_fixup(struct mei_cl_device *dev);
343*4882a593Smuzhiyun ssize_t __mei_cl_send(struct mei_cl *cl, u8 *buf, size_t length,
344*4882a593Smuzhiyun 		      unsigned int mode);
345*4882a593Smuzhiyun ssize_t __mei_cl_recv(struct mei_cl *cl, u8 *buf, size_t length,
346*4882a593Smuzhiyun 		      unsigned int mode, unsigned long timeout);
347*4882a593Smuzhiyun bool mei_cl_bus_rx_event(struct mei_cl *cl);
348*4882a593Smuzhiyun bool mei_cl_bus_notify_event(struct mei_cl *cl);
349*4882a593Smuzhiyun void mei_cl_bus_remove_devices(struct mei_device *bus);
350*4882a593Smuzhiyun int mei_cl_bus_init(void);
351*4882a593Smuzhiyun void mei_cl_bus_exit(void);
352*4882a593Smuzhiyun 
353*4882a593Smuzhiyun /**
354*4882a593Smuzhiyun  * enum mei_pg_event - power gating transition events
355*4882a593Smuzhiyun  *
356*4882a593Smuzhiyun  * @MEI_PG_EVENT_IDLE: the driver is not in power gating transition
357*4882a593Smuzhiyun  * @MEI_PG_EVENT_WAIT: the driver is waiting for a pg event to complete
358*4882a593Smuzhiyun  * @MEI_PG_EVENT_RECEIVED: the driver received pg event
359*4882a593Smuzhiyun  * @MEI_PG_EVENT_INTR_WAIT: the driver is waiting for a pg event interrupt
360*4882a593Smuzhiyun  * @MEI_PG_EVENT_INTR_RECEIVED: the driver received pg event interrupt
361*4882a593Smuzhiyun  */
362*4882a593Smuzhiyun enum mei_pg_event {
363*4882a593Smuzhiyun 	MEI_PG_EVENT_IDLE,
364*4882a593Smuzhiyun 	MEI_PG_EVENT_WAIT,
365*4882a593Smuzhiyun 	MEI_PG_EVENT_RECEIVED,
366*4882a593Smuzhiyun 	MEI_PG_EVENT_INTR_WAIT,
367*4882a593Smuzhiyun 	MEI_PG_EVENT_INTR_RECEIVED,
368*4882a593Smuzhiyun };
369*4882a593Smuzhiyun 
370*4882a593Smuzhiyun /**
371*4882a593Smuzhiyun  * enum mei_pg_state - device internal power gating state
372*4882a593Smuzhiyun  *
373*4882a593Smuzhiyun  * @MEI_PG_OFF: device is not power gated - it is active
374*4882a593Smuzhiyun  * @MEI_PG_ON:  device is power gated - it is in lower power state
375*4882a593Smuzhiyun  */
376*4882a593Smuzhiyun enum mei_pg_state {
377*4882a593Smuzhiyun 	MEI_PG_OFF = 0,
378*4882a593Smuzhiyun 	MEI_PG_ON =  1,
379*4882a593Smuzhiyun };
380*4882a593Smuzhiyun 
381*4882a593Smuzhiyun const char *mei_pg_state_str(enum mei_pg_state state);
382*4882a593Smuzhiyun 
383*4882a593Smuzhiyun /**
384*4882a593Smuzhiyun  * struct mei_fw_version - MEI FW version struct
385*4882a593Smuzhiyun  *
386*4882a593Smuzhiyun  * @platform: platform identifier
387*4882a593Smuzhiyun  * @major: major version field
388*4882a593Smuzhiyun  * @minor: minor version field
389*4882a593Smuzhiyun  * @buildno: build number version field
390*4882a593Smuzhiyun  * @hotfix: hotfix number version field
391*4882a593Smuzhiyun  */
392*4882a593Smuzhiyun struct mei_fw_version {
393*4882a593Smuzhiyun 	u8 platform;
394*4882a593Smuzhiyun 	u8 major;
395*4882a593Smuzhiyun 	u16 minor;
396*4882a593Smuzhiyun 	u16 buildno;
397*4882a593Smuzhiyun 	u16 hotfix;
398*4882a593Smuzhiyun };
399*4882a593Smuzhiyun 
400*4882a593Smuzhiyun #define MEI_MAX_FW_VER_BLOCKS 3
401*4882a593Smuzhiyun 
402*4882a593Smuzhiyun /**
403*4882a593Smuzhiyun  * struct mei_device -  MEI private device struct
404*4882a593Smuzhiyun  *
405*4882a593Smuzhiyun  * @dev         : device on a bus
406*4882a593Smuzhiyun  * @cdev        : character device
407*4882a593Smuzhiyun  * @minor       : minor number allocated for device
408*4882a593Smuzhiyun  *
409*4882a593Smuzhiyun  * @write_list  : write pending list
410*4882a593Smuzhiyun  * @write_waiting_list : write completion list
411*4882a593Smuzhiyun  * @ctrl_wr_list : pending control write list
412*4882a593Smuzhiyun  * @ctrl_rd_list : pending control read list
413*4882a593Smuzhiyun  * @tx_queue_limit: tx queues per client linit
414*4882a593Smuzhiyun  *
415*4882a593Smuzhiyun  * @file_list   : list of opened handles
416*4882a593Smuzhiyun  * @open_handle_count: number of opened handles
417*4882a593Smuzhiyun  *
418*4882a593Smuzhiyun  * @device_lock : big device lock
419*4882a593Smuzhiyun  * @timer_work  : MEI timer delayed work (timeouts)
420*4882a593Smuzhiyun  *
421*4882a593Smuzhiyun  * @recvd_hw_ready : hw ready message received flag
422*4882a593Smuzhiyun  *
423*4882a593Smuzhiyun  * @wait_hw_ready : wait queue for receive HW ready message form FW
424*4882a593Smuzhiyun  * @wait_pg     : wait queue for receive PG message from FW
425*4882a593Smuzhiyun  * @wait_hbm_start : wait queue for receive HBM start message from FW
426*4882a593Smuzhiyun  *
427*4882a593Smuzhiyun  * @reset_count : number of consecutive resets
428*4882a593Smuzhiyun  * @dev_state   : device state
429*4882a593Smuzhiyun  * @hbm_state   : state of host bus message protocol
430*4882a593Smuzhiyun  * @init_clients_timer : HBM init handshake timeout
431*4882a593Smuzhiyun  *
432*4882a593Smuzhiyun  * @pg_event    : power gating event
433*4882a593Smuzhiyun  * @pg_domain   : runtime PM domain
434*4882a593Smuzhiyun  *
435*4882a593Smuzhiyun  * @rd_msg_buf  : control messages buffer
436*4882a593Smuzhiyun  * @rd_msg_hdr  : read message header storage
437*4882a593Smuzhiyun  * @rd_msg_hdr_count : how many dwords were already read from header
438*4882a593Smuzhiyun  *
439*4882a593Smuzhiyun  * @hbuf_is_ready : query if the host host/write buffer is ready
440*4882a593Smuzhiyun  * @dr_dscr: DMA ring descriptors: TX, RX, and CTRL
441*4882a593Smuzhiyun  *
442*4882a593Smuzhiyun  * @version     : HBM protocol version in use
443*4882a593Smuzhiyun  * @hbm_f_pg_supported  : hbm feature pgi protocol
444*4882a593Smuzhiyun  * @hbm_f_dc_supported  : hbm feature dynamic clients
445*4882a593Smuzhiyun  * @hbm_f_dot_supported : hbm feature disconnect on timeout
446*4882a593Smuzhiyun  * @hbm_f_ev_supported  : hbm feature event notification
447*4882a593Smuzhiyun  * @hbm_f_fa_supported  : hbm feature fixed address client
448*4882a593Smuzhiyun  * @hbm_f_ie_supported  : hbm feature immediate reply to enum request
449*4882a593Smuzhiyun  * @hbm_f_os_supported  : hbm feature support OS ver message
450*4882a593Smuzhiyun  * @hbm_f_dr_supported  : hbm feature dma ring supported
451*4882a593Smuzhiyun  * @hbm_f_vt_supported  : hbm feature vtag supported
452*4882a593Smuzhiyun  * @hbm_f_cap_supported : hbm feature capabilities message supported
453*4882a593Smuzhiyun  *
454*4882a593Smuzhiyun  * @fw_ver : FW versions
455*4882a593Smuzhiyun  *
456*4882a593Smuzhiyun  * @fw_f_fw_ver_supported : fw feature: fw version supported
457*4882a593Smuzhiyun  *
458*4882a593Smuzhiyun  * @me_clients_rwsem: rw lock over me_clients list
459*4882a593Smuzhiyun  * @me_clients  : list of FW clients
460*4882a593Smuzhiyun  * @me_clients_map : FW clients bit map
461*4882a593Smuzhiyun  * @host_clients_map : host clients id pool
462*4882a593Smuzhiyun  *
463*4882a593Smuzhiyun  * @allow_fixed_address: allow user space to connect a fixed client
464*4882a593Smuzhiyun  * @override_fixed_address: force allow fixed address behavior
465*4882a593Smuzhiyun  *
466*4882a593Smuzhiyun  * @reset_work  : work item for the device reset
467*4882a593Smuzhiyun  * @bus_rescan_work : work item for the bus rescan
468*4882a593Smuzhiyun  *
469*4882a593Smuzhiyun  * @device_list : mei client bus list
470*4882a593Smuzhiyun  * @cl_bus_lock : client bus list lock
471*4882a593Smuzhiyun  *
472*4882a593Smuzhiyun  * @kind        : kind of mei device
473*4882a593Smuzhiyun  *
474*4882a593Smuzhiyun  * @dbgfs_dir   : debugfs mei root directory
475*4882a593Smuzhiyun  *
476*4882a593Smuzhiyun  * @ops:        : hw specific operations
477*4882a593Smuzhiyun  * @hw          : hw specific data
478*4882a593Smuzhiyun  */
479*4882a593Smuzhiyun struct mei_device {
480*4882a593Smuzhiyun 	struct device *dev;
481*4882a593Smuzhiyun 	struct cdev cdev;
482*4882a593Smuzhiyun 	int minor;
483*4882a593Smuzhiyun 
484*4882a593Smuzhiyun 	struct list_head write_list;
485*4882a593Smuzhiyun 	struct list_head write_waiting_list;
486*4882a593Smuzhiyun 	struct list_head ctrl_wr_list;
487*4882a593Smuzhiyun 	struct list_head ctrl_rd_list;
488*4882a593Smuzhiyun 	u8 tx_queue_limit;
489*4882a593Smuzhiyun 
490*4882a593Smuzhiyun 	struct list_head file_list;
491*4882a593Smuzhiyun 	long open_handle_count;
492*4882a593Smuzhiyun 
493*4882a593Smuzhiyun 	struct mutex device_lock;
494*4882a593Smuzhiyun 	struct delayed_work timer_work;
495*4882a593Smuzhiyun 
496*4882a593Smuzhiyun 	bool recvd_hw_ready;
497*4882a593Smuzhiyun 	/*
498*4882a593Smuzhiyun 	 * waiting queue for receive message from FW
499*4882a593Smuzhiyun 	 */
500*4882a593Smuzhiyun 	wait_queue_head_t wait_hw_ready;
501*4882a593Smuzhiyun 	wait_queue_head_t wait_pg;
502*4882a593Smuzhiyun 	wait_queue_head_t wait_hbm_start;
503*4882a593Smuzhiyun 
504*4882a593Smuzhiyun 	/*
505*4882a593Smuzhiyun 	 * mei device  states
506*4882a593Smuzhiyun 	 */
507*4882a593Smuzhiyun 	unsigned long reset_count;
508*4882a593Smuzhiyun 	enum mei_dev_state dev_state;
509*4882a593Smuzhiyun 	enum mei_hbm_state hbm_state;
510*4882a593Smuzhiyun 	u16 init_clients_timer;
511*4882a593Smuzhiyun 
512*4882a593Smuzhiyun 	/*
513*4882a593Smuzhiyun 	 * Power Gating support
514*4882a593Smuzhiyun 	 */
515*4882a593Smuzhiyun 	enum mei_pg_event pg_event;
516*4882a593Smuzhiyun #ifdef CONFIG_PM
517*4882a593Smuzhiyun 	struct dev_pm_domain pg_domain;
518*4882a593Smuzhiyun #endif /* CONFIG_PM */
519*4882a593Smuzhiyun 
520*4882a593Smuzhiyun 	unsigned char rd_msg_buf[MEI_RD_MSG_BUF_SIZE];
521*4882a593Smuzhiyun 	u32 rd_msg_hdr[MEI_RD_MSG_BUF_SIZE];
522*4882a593Smuzhiyun 	int rd_msg_hdr_count;
523*4882a593Smuzhiyun 
524*4882a593Smuzhiyun 	/* write buffer */
525*4882a593Smuzhiyun 	bool hbuf_is_ready;
526*4882a593Smuzhiyun 
527*4882a593Smuzhiyun 	struct mei_dma_dscr dr_dscr[DMA_DSCR_NUM];
528*4882a593Smuzhiyun 
529*4882a593Smuzhiyun 	struct hbm_version version;
530*4882a593Smuzhiyun 	unsigned int hbm_f_pg_supported:1;
531*4882a593Smuzhiyun 	unsigned int hbm_f_dc_supported:1;
532*4882a593Smuzhiyun 	unsigned int hbm_f_dot_supported:1;
533*4882a593Smuzhiyun 	unsigned int hbm_f_ev_supported:1;
534*4882a593Smuzhiyun 	unsigned int hbm_f_fa_supported:1;
535*4882a593Smuzhiyun 	unsigned int hbm_f_ie_supported:1;
536*4882a593Smuzhiyun 	unsigned int hbm_f_os_supported:1;
537*4882a593Smuzhiyun 	unsigned int hbm_f_dr_supported:1;
538*4882a593Smuzhiyun 	unsigned int hbm_f_vt_supported:1;
539*4882a593Smuzhiyun 	unsigned int hbm_f_cap_supported:1;
540*4882a593Smuzhiyun 
541*4882a593Smuzhiyun 	struct mei_fw_version fw_ver[MEI_MAX_FW_VER_BLOCKS];
542*4882a593Smuzhiyun 
543*4882a593Smuzhiyun 	unsigned int fw_f_fw_ver_supported:1;
544*4882a593Smuzhiyun 
545*4882a593Smuzhiyun 	struct rw_semaphore me_clients_rwsem;
546*4882a593Smuzhiyun 	struct list_head me_clients;
547*4882a593Smuzhiyun 	DECLARE_BITMAP(me_clients_map, MEI_CLIENTS_MAX);
548*4882a593Smuzhiyun 	DECLARE_BITMAP(host_clients_map, MEI_CLIENTS_MAX);
549*4882a593Smuzhiyun 
550*4882a593Smuzhiyun 	bool allow_fixed_address;
551*4882a593Smuzhiyun 	bool override_fixed_address;
552*4882a593Smuzhiyun 
553*4882a593Smuzhiyun 	struct work_struct reset_work;
554*4882a593Smuzhiyun 	struct work_struct bus_rescan_work;
555*4882a593Smuzhiyun 
556*4882a593Smuzhiyun 	/* List of bus devices */
557*4882a593Smuzhiyun 	struct list_head device_list;
558*4882a593Smuzhiyun 	struct mutex cl_bus_lock;
559*4882a593Smuzhiyun 
560*4882a593Smuzhiyun 	const char *kind;
561*4882a593Smuzhiyun 
562*4882a593Smuzhiyun #if IS_ENABLED(CONFIG_DEBUG_FS)
563*4882a593Smuzhiyun 	struct dentry *dbgfs_dir;
564*4882a593Smuzhiyun #endif /* CONFIG_DEBUG_FS */
565*4882a593Smuzhiyun 
566*4882a593Smuzhiyun 	const struct mei_hw_ops *ops;
567*4882a593Smuzhiyun 	char hw[] __aligned(sizeof(void *));
568*4882a593Smuzhiyun };
569*4882a593Smuzhiyun 
mei_secs_to_jiffies(unsigned long sec)570*4882a593Smuzhiyun static inline unsigned long mei_secs_to_jiffies(unsigned long sec)
571*4882a593Smuzhiyun {
572*4882a593Smuzhiyun 	return msecs_to_jiffies(sec * MSEC_PER_SEC);
573*4882a593Smuzhiyun }
574*4882a593Smuzhiyun 
575*4882a593Smuzhiyun /**
576*4882a593Smuzhiyun  * mei_data2slots - get slots number from a message length
577*4882a593Smuzhiyun  *
578*4882a593Smuzhiyun  * @length: size of the messages in bytes
579*4882a593Smuzhiyun  *
580*4882a593Smuzhiyun  * Return: number of slots
581*4882a593Smuzhiyun  */
mei_data2slots(size_t length)582*4882a593Smuzhiyun static inline u32 mei_data2slots(size_t length)
583*4882a593Smuzhiyun {
584*4882a593Smuzhiyun 	return DIV_ROUND_UP(length, MEI_SLOT_SIZE);
585*4882a593Smuzhiyun }
586*4882a593Smuzhiyun 
587*4882a593Smuzhiyun /**
588*4882a593Smuzhiyun  * mei_hbm2slots - get slots number from a hbm message length
589*4882a593Smuzhiyun  *                 length + size of the mei message header
590*4882a593Smuzhiyun  *
591*4882a593Smuzhiyun  * @length: size of the messages in bytes
592*4882a593Smuzhiyun  *
593*4882a593Smuzhiyun  * Return: number of slots
594*4882a593Smuzhiyun  */
mei_hbm2slots(size_t length)595*4882a593Smuzhiyun static inline u32 mei_hbm2slots(size_t length)
596*4882a593Smuzhiyun {
597*4882a593Smuzhiyun 	return DIV_ROUND_UP(sizeof(struct mei_msg_hdr) + length, MEI_SLOT_SIZE);
598*4882a593Smuzhiyun }
599*4882a593Smuzhiyun 
600*4882a593Smuzhiyun /**
601*4882a593Smuzhiyun  * mei_slots2data - get data in slots - bytes from slots
602*4882a593Smuzhiyun  *
603*4882a593Smuzhiyun  * @slots: number of available slots
604*4882a593Smuzhiyun  *
605*4882a593Smuzhiyun  * Return: number of bytes in slots
606*4882a593Smuzhiyun  */
mei_slots2data(int slots)607*4882a593Smuzhiyun static inline u32 mei_slots2data(int slots)
608*4882a593Smuzhiyun {
609*4882a593Smuzhiyun 	return slots * MEI_SLOT_SIZE;
610*4882a593Smuzhiyun }
611*4882a593Smuzhiyun 
612*4882a593Smuzhiyun /*
613*4882a593Smuzhiyun  * mei init function prototypes
614*4882a593Smuzhiyun  */
615*4882a593Smuzhiyun void mei_device_init(struct mei_device *dev,
616*4882a593Smuzhiyun 		     struct device *device,
617*4882a593Smuzhiyun 		     const struct mei_hw_ops *hw_ops);
618*4882a593Smuzhiyun int mei_reset(struct mei_device *dev);
619*4882a593Smuzhiyun int mei_start(struct mei_device *dev);
620*4882a593Smuzhiyun int mei_restart(struct mei_device *dev);
621*4882a593Smuzhiyun void mei_stop(struct mei_device *dev);
622*4882a593Smuzhiyun void mei_cancel_work(struct mei_device *dev);
623*4882a593Smuzhiyun 
624*4882a593Smuzhiyun void mei_set_devstate(struct mei_device *dev, enum mei_dev_state state);
625*4882a593Smuzhiyun 
626*4882a593Smuzhiyun int mei_dmam_ring_alloc(struct mei_device *dev);
627*4882a593Smuzhiyun void mei_dmam_ring_free(struct mei_device *dev);
628*4882a593Smuzhiyun bool mei_dma_ring_is_allocated(struct mei_device *dev);
629*4882a593Smuzhiyun void mei_dma_ring_reset(struct mei_device *dev);
630*4882a593Smuzhiyun void mei_dma_ring_read(struct mei_device *dev, unsigned char *buf, u32 len);
631*4882a593Smuzhiyun void mei_dma_ring_write(struct mei_device *dev, unsigned char *buf, u32 len);
632*4882a593Smuzhiyun u32 mei_dma_ring_empty_slots(struct mei_device *dev);
633*4882a593Smuzhiyun 
634*4882a593Smuzhiyun /*
635*4882a593Smuzhiyun  *  MEI interrupt functions prototype
636*4882a593Smuzhiyun  */
637*4882a593Smuzhiyun 
638*4882a593Smuzhiyun void mei_timer(struct work_struct *work);
639*4882a593Smuzhiyun void mei_schedule_stall_timer(struct mei_device *dev);
640*4882a593Smuzhiyun int mei_irq_read_handler(struct mei_device *dev,
641*4882a593Smuzhiyun 			 struct list_head *cmpl_list, s32 *slots);
642*4882a593Smuzhiyun 
643*4882a593Smuzhiyun int mei_irq_write_handler(struct mei_device *dev, struct list_head *cmpl_list);
644*4882a593Smuzhiyun void mei_irq_compl_handler(struct mei_device *dev, struct list_head *cmpl_list);
645*4882a593Smuzhiyun 
646*4882a593Smuzhiyun /*
647*4882a593Smuzhiyun  * Register Access Function
648*4882a593Smuzhiyun  */
649*4882a593Smuzhiyun 
650*4882a593Smuzhiyun 
mei_hw_config(struct mei_device * dev)651*4882a593Smuzhiyun static inline int mei_hw_config(struct mei_device *dev)
652*4882a593Smuzhiyun {
653*4882a593Smuzhiyun 	return dev->ops->hw_config(dev);
654*4882a593Smuzhiyun }
655*4882a593Smuzhiyun 
mei_pg_state(struct mei_device * dev)656*4882a593Smuzhiyun static inline enum mei_pg_state mei_pg_state(struct mei_device *dev)
657*4882a593Smuzhiyun {
658*4882a593Smuzhiyun 	return dev->ops->pg_state(dev);
659*4882a593Smuzhiyun }
660*4882a593Smuzhiyun 
mei_pg_in_transition(struct mei_device * dev)661*4882a593Smuzhiyun static inline bool mei_pg_in_transition(struct mei_device *dev)
662*4882a593Smuzhiyun {
663*4882a593Smuzhiyun 	return dev->ops->pg_in_transition(dev);
664*4882a593Smuzhiyun }
665*4882a593Smuzhiyun 
mei_pg_is_enabled(struct mei_device * dev)666*4882a593Smuzhiyun static inline bool mei_pg_is_enabled(struct mei_device *dev)
667*4882a593Smuzhiyun {
668*4882a593Smuzhiyun 	return dev->ops->pg_is_enabled(dev);
669*4882a593Smuzhiyun }
670*4882a593Smuzhiyun 
mei_hw_reset(struct mei_device * dev,bool enable)671*4882a593Smuzhiyun static inline int mei_hw_reset(struct mei_device *dev, bool enable)
672*4882a593Smuzhiyun {
673*4882a593Smuzhiyun 	return dev->ops->hw_reset(dev, enable);
674*4882a593Smuzhiyun }
675*4882a593Smuzhiyun 
mei_hw_start(struct mei_device * dev)676*4882a593Smuzhiyun static inline int mei_hw_start(struct mei_device *dev)
677*4882a593Smuzhiyun {
678*4882a593Smuzhiyun 	return dev->ops->hw_start(dev);
679*4882a593Smuzhiyun }
680*4882a593Smuzhiyun 
mei_clear_interrupts(struct mei_device * dev)681*4882a593Smuzhiyun static inline void mei_clear_interrupts(struct mei_device *dev)
682*4882a593Smuzhiyun {
683*4882a593Smuzhiyun 	dev->ops->intr_clear(dev);
684*4882a593Smuzhiyun }
685*4882a593Smuzhiyun 
mei_enable_interrupts(struct mei_device * dev)686*4882a593Smuzhiyun static inline void mei_enable_interrupts(struct mei_device *dev)
687*4882a593Smuzhiyun {
688*4882a593Smuzhiyun 	dev->ops->intr_enable(dev);
689*4882a593Smuzhiyun }
690*4882a593Smuzhiyun 
mei_disable_interrupts(struct mei_device * dev)691*4882a593Smuzhiyun static inline void mei_disable_interrupts(struct mei_device *dev)
692*4882a593Smuzhiyun {
693*4882a593Smuzhiyun 	dev->ops->intr_disable(dev);
694*4882a593Smuzhiyun }
695*4882a593Smuzhiyun 
mei_synchronize_irq(struct mei_device * dev)696*4882a593Smuzhiyun static inline void mei_synchronize_irq(struct mei_device *dev)
697*4882a593Smuzhiyun {
698*4882a593Smuzhiyun 	dev->ops->synchronize_irq(dev);
699*4882a593Smuzhiyun }
700*4882a593Smuzhiyun 
mei_host_is_ready(struct mei_device * dev)701*4882a593Smuzhiyun static inline bool mei_host_is_ready(struct mei_device *dev)
702*4882a593Smuzhiyun {
703*4882a593Smuzhiyun 	return dev->ops->host_is_ready(dev);
704*4882a593Smuzhiyun }
mei_hw_is_ready(struct mei_device * dev)705*4882a593Smuzhiyun static inline bool mei_hw_is_ready(struct mei_device *dev)
706*4882a593Smuzhiyun {
707*4882a593Smuzhiyun 	return dev->ops->hw_is_ready(dev);
708*4882a593Smuzhiyun }
709*4882a593Smuzhiyun 
mei_hbuf_is_ready(struct mei_device * dev)710*4882a593Smuzhiyun static inline bool mei_hbuf_is_ready(struct mei_device *dev)
711*4882a593Smuzhiyun {
712*4882a593Smuzhiyun 	return dev->ops->hbuf_is_ready(dev);
713*4882a593Smuzhiyun }
714*4882a593Smuzhiyun 
mei_hbuf_empty_slots(struct mei_device * dev)715*4882a593Smuzhiyun static inline int mei_hbuf_empty_slots(struct mei_device *dev)
716*4882a593Smuzhiyun {
717*4882a593Smuzhiyun 	return dev->ops->hbuf_free_slots(dev);
718*4882a593Smuzhiyun }
719*4882a593Smuzhiyun 
mei_hbuf_depth(const struct mei_device * dev)720*4882a593Smuzhiyun static inline u32 mei_hbuf_depth(const struct mei_device *dev)
721*4882a593Smuzhiyun {
722*4882a593Smuzhiyun 	return dev->ops->hbuf_depth(dev);
723*4882a593Smuzhiyun }
724*4882a593Smuzhiyun 
mei_write_message(struct mei_device * dev,const void * hdr,size_t hdr_len,const void * data,size_t data_len)725*4882a593Smuzhiyun static inline int mei_write_message(struct mei_device *dev,
726*4882a593Smuzhiyun 				    const void *hdr, size_t hdr_len,
727*4882a593Smuzhiyun 				    const void *data, size_t data_len)
728*4882a593Smuzhiyun {
729*4882a593Smuzhiyun 	return dev->ops->write(dev, hdr, hdr_len, data, data_len);
730*4882a593Smuzhiyun }
731*4882a593Smuzhiyun 
mei_read_hdr(const struct mei_device * dev)732*4882a593Smuzhiyun static inline u32 mei_read_hdr(const struct mei_device *dev)
733*4882a593Smuzhiyun {
734*4882a593Smuzhiyun 	return dev->ops->read_hdr(dev);
735*4882a593Smuzhiyun }
736*4882a593Smuzhiyun 
mei_read_slots(struct mei_device * dev,unsigned char * buf,unsigned long len)737*4882a593Smuzhiyun static inline void mei_read_slots(struct mei_device *dev,
738*4882a593Smuzhiyun 		     unsigned char *buf, unsigned long len)
739*4882a593Smuzhiyun {
740*4882a593Smuzhiyun 	dev->ops->read(dev, buf, len);
741*4882a593Smuzhiyun }
742*4882a593Smuzhiyun 
mei_count_full_read_slots(struct mei_device * dev)743*4882a593Smuzhiyun static inline int mei_count_full_read_slots(struct mei_device *dev)
744*4882a593Smuzhiyun {
745*4882a593Smuzhiyun 	return dev->ops->rdbuf_full_slots(dev);
746*4882a593Smuzhiyun }
747*4882a593Smuzhiyun 
mei_trc_status(struct mei_device * dev,u32 * trc)748*4882a593Smuzhiyun static inline int mei_trc_status(struct mei_device *dev, u32 *trc)
749*4882a593Smuzhiyun {
750*4882a593Smuzhiyun 	if (dev->ops->trc_status)
751*4882a593Smuzhiyun 		return dev->ops->trc_status(dev, trc);
752*4882a593Smuzhiyun 	return -EOPNOTSUPP;
753*4882a593Smuzhiyun }
754*4882a593Smuzhiyun 
mei_fw_status(struct mei_device * dev,struct mei_fw_status * fw_status)755*4882a593Smuzhiyun static inline int mei_fw_status(struct mei_device *dev,
756*4882a593Smuzhiyun 				struct mei_fw_status *fw_status)
757*4882a593Smuzhiyun {
758*4882a593Smuzhiyun 	return dev->ops->fw_status(dev, fw_status);
759*4882a593Smuzhiyun }
760*4882a593Smuzhiyun 
761*4882a593Smuzhiyun bool mei_hbuf_acquire(struct mei_device *dev);
762*4882a593Smuzhiyun 
763*4882a593Smuzhiyun bool mei_write_is_idle(struct mei_device *dev);
764*4882a593Smuzhiyun 
765*4882a593Smuzhiyun #if IS_ENABLED(CONFIG_DEBUG_FS)
766*4882a593Smuzhiyun void mei_dbgfs_register(struct mei_device *dev, const char *name);
767*4882a593Smuzhiyun void mei_dbgfs_deregister(struct mei_device *dev);
768*4882a593Smuzhiyun #else
mei_dbgfs_register(struct mei_device * dev,const char * name)769*4882a593Smuzhiyun static inline void mei_dbgfs_register(struct mei_device *dev, const char *name) {}
mei_dbgfs_deregister(struct mei_device * dev)770*4882a593Smuzhiyun static inline void mei_dbgfs_deregister(struct mei_device *dev) {}
771*4882a593Smuzhiyun #endif /* CONFIG_DEBUG_FS */
772*4882a593Smuzhiyun 
773*4882a593Smuzhiyun int mei_register(struct mei_device *dev, struct device *parent);
774*4882a593Smuzhiyun void mei_deregister(struct mei_device *dev);
775*4882a593Smuzhiyun 
776*4882a593Smuzhiyun #define MEI_HDR_FMT "hdr:host=%02d me=%02d len=%d dma=%1d ext=%1d internal=%1d comp=%1d"
777*4882a593Smuzhiyun #define MEI_HDR_PRM(hdr)                  \
778*4882a593Smuzhiyun 	(hdr)->host_addr, (hdr)->me_addr, \
779*4882a593Smuzhiyun 	(hdr)->length, (hdr)->dma_ring, (hdr)->extended, \
780*4882a593Smuzhiyun 	(hdr)->internal, (hdr)->msg_complete
781*4882a593Smuzhiyun 
782*4882a593Smuzhiyun ssize_t mei_fw_status2str(struct mei_fw_status *fw_sts, char *buf, size_t len);
783*4882a593Smuzhiyun /**
784*4882a593Smuzhiyun  * mei_fw_status_str - fetch and convert fw status registers to printable string
785*4882a593Smuzhiyun  *
786*4882a593Smuzhiyun  * @dev: the device structure
787*4882a593Smuzhiyun  * @buf: string buffer at minimal size MEI_FW_STATUS_STR_SZ
788*4882a593Smuzhiyun  * @len: buffer len must be >= MEI_FW_STATUS_STR_SZ
789*4882a593Smuzhiyun  *
790*4882a593Smuzhiyun  * Return: number of bytes written or < 0 on failure
791*4882a593Smuzhiyun  */
mei_fw_status_str(struct mei_device * dev,char * buf,size_t len)792*4882a593Smuzhiyun static inline ssize_t mei_fw_status_str(struct mei_device *dev,
793*4882a593Smuzhiyun 					char *buf, size_t len)
794*4882a593Smuzhiyun {
795*4882a593Smuzhiyun 	struct mei_fw_status fw_status;
796*4882a593Smuzhiyun 	int ret;
797*4882a593Smuzhiyun 
798*4882a593Smuzhiyun 	buf[0] = '\0';
799*4882a593Smuzhiyun 
800*4882a593Smuzhiyun 	ret = mei_fw_status(dev, &fw_status);
801*4882a593Smuzhiyun 	if (ret)
802*4882a593Smuzhiyun 		return ret;
803*4882a593Smuzhiyun 
804*4882a593Smuzhiyun 	ret = mei_fw_status2str(&fw_status, buf, MEI_FW_STATUS_STR_SZ);
805*4882a593Smuzhiyun 
806*4882a593Smuzhiyun 	return ret;
807*4882a593Smuzhiyun }
808*4882a593Smuzhiyun 
809*4882a593Smuzhiyun 
810*4882a593Smuzhiyun #endif
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