1*4882a593SmuzhiyunDevice Tree Clock bindings for ZTE zx296702 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunThis binding uses the common clock binding[1]. 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun[1] Documentation/devicetree/bindings/clock/clock-bindings.txt 6*4882a593Smuzhiyun 7*4882a593SmuzhiyunRequired properties: 8*4882a593Smuzhiyun- compatible : shall be one of the following: 9*4882a593Smuzhiyun "zte,zx296702-topcrm-clk": 10*4882a593Smuzhiyun zx296702 top clock selection, divider and gating 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun "zte,zx296702-lsp0crpm-clk" and 13*4882a593Smuzhiyun "zte,zx296702-lsp1crpm-clk": 14*4882a593Smuzhiyun zx296702 device level clock selection and gating 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun- reg: Address and length of the register set 17*4882a593Smuzhiyun 18*4882a593SmuzhiyunThe clock consumer should specify the desired clock by having the clock 19*4882a593SmuzhiyunID in its "clocks" phandle cell. See include/dt-bindings/clock/zx296702-clock.h 20*4882a593Smuzhiyunfor the full list of zx296702 clock IDs. 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun 23*4882a593Smuzhiyuntopclk: topcrm@09800000 { 24*4882a593Smuzhiyun compatible = "zte,zx296702-topcrm-clk"; 25*4882a593Smuzhiyun reg = <0x09800000 0x1000>; 26*4882a593Smuzhiyun #clock-cells = <1>; 27*4882a593Smuzhiyun}; 28*4882a593Smuzhiyun 29*4882a593Smuzhiyunuart0: serial@09405000 { 30*4882a593Smuzhiyun compatible = "zte,zx296702-uart"; 31*4882a593Smuzhiyun reg = <0x09405000 0x1000>; 32*4882a593Smuzhiyun interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 33*4882a593Smuzhiyun clocks = <&lsp1clk ZX296702_UART0_PCLK>; 34*4882a593Smuzhiyun}; 35