1*4882a593SmuzhiyunDevice Tree Clock bindings for ZTE zx296718 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunThis binding uses the common clock binding[1]. 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun[1] Documentation/devicetree/bindings/clock/clock-bindings.txt 6*4882a593Smuzhiyun 7*4882a593SmuzhiyunRequired properties: 8*4882a593Smuzhiyun- compatible : shall be one of the following: 9*4882a593Smuzhiyun "zte,zx296718-topcrm": 10*4882a593Smuzhiyun zx296718 top clock selection, divider and gating 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun "zte,zx296718-lsp0crm" and 13*4882a593Smuzhiyun "zte,zx296718-lsp1crm": 14*4882a593Smuzhiyun zx296718 device level clock selection and gating 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun "zte,zx296718-audiocrm": 17*4882a593Smuzhiyun zx296718 audio clock selection, divider and gating 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun- reg: Address and length of the register set 20*4882a593Smuzhiyun 21*4882a593SmuzhiyunThe clock consumer should specify the desired clock by having the clock 22*4882a593SmuzhiyunID in its "clocks" phandle cell. See include/dt-bindings/clock/zx296718-clock.h 23*4882a593Smuzhiyunfor the full list of zx296718 clock IDs. 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun 26*4882a593Smuzhiyuntopclk: topcrm@1461000 { 27*4882a593Smuzhiyun compatible = "zte,zx296718-topcrm-clk"; 28*4882a593Smuzhiyun reg = <0x01461000 0x1000>; 29*4882a593Smuzhiyun #clock-cells = <1>; 30*4882a593Smuzhiyun}; 31*4882a593Smuzhiyun 32*4882a593Smuzhiyunusbphy0:usb-phy0 { 33*4882a593Smuzhiyun compatible = "zte,zx296718-usb-phy"; 34*4882a593Smuzhiyun #phy-cells = <0>; 35*4882a593Smuzhiyun clocks = <&topclk USB20_PHY_CLK>; 36*4882a593Smuzhiyun clock-names = "phyclk"; 37*4882a593Smuzhiyun}; 38