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/OK3568_Linux_fs/buildroot/arch/
H A DConfig.in.arm146 bool "arm1136j-s"
152 bool "arm1136jf-s"
159 bool "arm1176jz-s"
165 bool "arm1176jzf-s"
181 bool "cortex-A5"
189 bool "cortex-A7"
197 bool "cortex-A8"
205 bool "cortex-A9"
213 bool "cortex-A12"
221 bool "cortex-A15"
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/arm/
H A Dpmu.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Mark Rutland <mark.rutland@arm.com>
11 - Will Deacon <will.deacon@arm.com>
14 ARM cores often have a PMU for counting cpu and cache events like cache misses
16 representation in the device tree should be done as under:-
21 - enum:
22 - apm,potenza-pmu
23 - arm,armv8-pmuv3 # Only for s/w models
[all …]
H A Dcpus.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
13 The device tree allows to describe the layout of CPUs in a system through
14 the "cpus" node, which in turn contains a number of subnodes (ie "cpu")
21 with updates for 32-bit and 64-bit ARM systems provided in this document.
30 - square brackets define bitfields, eg reg[7:0] value of the bitfield in
59 On 32-bit ARM v7 or later systems this property is
68 On ARM v8 64-bit systems this property is required
[all …]
H A Didle-states.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/arm/idle-states.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
14 1 - Introduction
18 where cores can be put in different low-power states (ranging from simple wfi
20 range of dynamic idle states that a processor can enter at run-time, can be
22 enter/exit specific idle states on a given processor.
27 - Running
[all …]
H A Dscu.txt3 As part of the MPCore complex, Cortex-A5 and Cortex-A9 are provided
4 with a Snoop Control Unit. The register range is usually 256 (0x100)
9 - Cortex-A9: see DDI0407E Cortex-A9 MPCore Technical Reference Manual
11 - Cortex-A5: see DDI0434B Cortex-A5 MPCore Technical Reference Manual
13 - ARM11 MPCore: see DDI0360F ARM 11 MPCore Processor Technical Reference
16 - compatible : Should be:
17 "arm,cortex-a9-scu"
18 "arm,cortex-a5-scu"
19 "arm,arm11mp-scu"
21 - reg : Specify the base address and the size of the SCU register window.
[all …]
H A Darm,vexpress-juno.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/arm/arm,vexpress-juno.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sudeep Holla <sudeep.holla@arm.com>
11 - Linus Walleij <linus.walleij@linaro.org>
15 multicore Cortex-A class systems. The Versatile Express family contains both
18 The board consist of a motherboard and one or more daughterboards (tiles). The
19 motherboard provides a set of peripherals. Processor and RAM "live" on the
22 The motherboard and each core tile should be described by a separate Device
[all …]
H A Darm,realview.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Linus Walleij <linus.walleij@linaro.org>
14 11, Cortex A-8 and Cortex A-9 CPUs. This included new features compared to
22 - description: ARM RealView Emulation Baseboard (HBI-0140) was created
23 as a generic platform to test different FPGA designs, and has
26 - const: arm,realview-eb
27 - description: ARM RealView Platform Baseboard for ARM1176JZF-S
28 (HBI-0147) was created as a development board to test ARM TrustZone,
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/OK3568_Linux_fs/yocto/poky/meta/recipes-devtools/valgrind/valgrind/
H A D0001-makefiles-Drop-setting-mcpu-to-cortex-a8-on-arm-arch.patch3 Date: Thu, 20 Apr 2017 10:11:16 -0700
4 Subject: [PATCH] makefiles: Drop setting -mcpu to cortex-a8 on arm
7 We can not assume that all arches armv7+ are cortex-a8 only
8 it fails to build for rpi which is armv7ve based (cortex-a8) cpu
11 | cc1: warning: switch -mcpu=cortex-a8 conflicts with -march=armv7ve switch
13 Upstream-Status: Submitted [https://bugs.kde.org/show_bug.cgi?id=454346]
15 Signed-off-by: Khem Raj <raj.khem@gmail.com>
16 ---
17 Makefile.all.am | 6 +++---
18 helgrind/tests/Makefile.am | 6 +++---
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H A Duse-appropriate-march-mcpu-mfpu-for-ARM-test-apps.patch3 Date: Tue, 19 Jan 2016 16:00:00 -0800
4 Subject: [PATCH] use appropriate -march/-mcpu/-mfpu for ARM test apps
7 -march/-mcpu/-mfpu flags to support the instructions being tested.
12 -march=armv7ve and -mcpu=cortex-a15 (since some TUNE_CCARGS may set
13 -march=armv7-a and adding -mcpu=cortex-a15 alone is not enough to
14 over-ride that).
18 Upstream-Status: Submitted [https://bugs.kde.org/show_bug.cgi?id=454346]
20 Signed-off-by: Andre McCurdy <armccurdy@gmail.com>
21 ---
22 none/tests/arm/Makefile.am | 6 ++++--
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/OK3568_Linux_fs/prebuilts/gcc/linux-x86/aarch64/gcc-arm-10.3-2021.07-x86_64-aarch64-none-linux-gnu/lib/gcc/aarch64-none-linux-gnu/10.3.1/plugin/include/config/aarch64/
H A Daarch64-cores.def1 /* Copyright (C) 2011-2020 Free Software Foundation, Inc.
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 You should have received a copy of the GNU General Public License
20 /* This is a list of cores that implement AArch64.
22 Before using #include to read this file, define a macro:
26 The CORE_NAME is the name of the core, represented as a string constant.
31 aarch64-arches.def.
32 FLAGS are the bitwise-or of the traits that apply to that core.
35 IMP is the implementer ID of the CPU vendor. On a GNU/Linux system it
36 can be found in /proc/cpuinfo. A partial list of implementer IDs is
[all …]
H A Daarch64-errata.h2 Copyright (C) 2009-2020 Free Software Foundation, Inc.
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 You should have received a copy of the GNU General Public License
26 " %{!mno-fix-cortex-a53-835769:--fix-cortex-a53-835769}"
29 " %{mfix-cortex-a53-835769:--fix-cortex-a53-835769}"
34 " %{!mno-fix-cortex-a53-843419:--fix-cortex-a53-843419}"
37 " %{mfix-cortex-a53-843419:--fix-cortex-a53-843419}"
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/cpu/
H A Dcpu-topology.txt6 1 - Introduction
9 In a SMP system, the hierarchy of CPUs is defined through three entities that
12 - socket
13 - cluster
14 - core
15 - thread
18 symmetric multi-threading (SMT) is supported or not.
20 For instance in a system where CPUs support SMT, "cpu" nodes represent all
29 Currently, only ARM/RISC-V intend to use this cpu topology binding but it may be
35 A topology description containing phandles to cpu nodes that are not compliant
[all …]
/OK3568_Linux_fs/prebuilts/gcc/linux-x86/arm/gcc-arm-10.3-2021.07-x86_64-arm-none-linux-gnueabihf/share/doc/as.html/
H A DAArch64-Options.html1 <!DOCTYPE html PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dt…
3 <!-- This file documents the GNU Assembler "as".
5 Copyright (C) 1991-2021 Free Software Foundation, Inc.
10 with no Invariant Sections, with no Front-Cover Texts, and with no
11 Back-Cover Texts. A copy of the license is included in the
13 -->
14 <!-- Created by GNU Texinfo 5.1, http://www.gnu.org/software/texinfo/ -->
20 <meta name="resource-type" content="document">
23 <meta http-equiv="Content-Type" content="text/html; charset=utf-8">
25 <link href="AS-Index.html#AS-Index" rel="index" title="AS Index">
[all …]
H A DARM-Options.html1 <!DOCTYPE html PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dt…
3 <!-- This file documents the GNU Assembler "as".
5 Copyright (C) 1991-2021 Free Software Foundation, Inc.
10 with no Invariant Sections, with no Front-Cover Texts, and with no
11 Back-Cover Texts. A copy of the license is included in the
13 -->
14 <!-- Created by GNU Texinfo 5.1, http://www.gnu.org/software/texinfo/ -->
20 <meta name="resource-type" content="document">
23 <meta http-equiv="Content-Type" content="text/html; charset=utf-8">
25 <link href="AS-Index.html#AS-Index" rel="index" title="AS Index">
[all …]
/OK3568_Linux_fs/prebuilts/gcc/linux-x86/aarch64/gcc-arm-10.3-2021.07-x86_64-aarch64-none-linux-gnu/share/doc/as.html/
H A DAArch64-Options.html1 <!DOCTYPE html PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dt…
3 <!-- This file documents the GNU Assembler "as".
5 Copyright (C) 1991-2021 Free Software Foundation, Inc.
10 with no Invariant Sections, with no Front-Cover Texts, and with no
11 Back-Cover Texts. A copy of the license is included in the
13 -->
14 <!-- Created by GNU Texinfo 5.1, http://www.gnu.org/software/texinfo/ -->
20 <meta name="resource-type" content="document">
23 <meta http-equiv="Content-Type" content="text/html; charset=utf-8">
25 <link href="AS-Index.html#AS-Index" rel="index" title="AS Index">
[all …]
H A DARM-Options.html1 <!DOCTYPE html PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dt…
3 <!-- This file documents the GNU Assembler "as".
5 Copyright (C) 1991-2021 Free Software Foundation, Inc.
10 with no Invariant Sections, with no Front-Cover Texts, and with no
11 Back-Cover Texts. A copy of the license is included in the
13 -->
14 <!-- Created by GNU Texinfo 5.1, http://www.gnu.org/software/texinfo/ -->
20 <meta name="resource-type" content="document">
23 <meta http-equiv="Content-Type" content="text/html; charset=utf-8">
25 <link href="AS-Index.html#AS-Index" rel="index" title="AS Index">
[all …]
/OK3568_Linux_fs/kernel/arch/arm64/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
168 if $(cc-option,-fpatchable-function-entry=2)
217 ARM 64-bit (AArch64) Linux support.
249 # VA_BITS - PAGE_SHIFT - 3
342 def_bool !$(as-instr,1:\n.inst 0\n.rept . - 1b\n\nnop\n.endr\n)
369 …bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is acce…
374 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
377 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
378 and is unable to accept a certain write via this interface, it will
383 data cache clean-and-invalidate.
[all …]
/OK3568_Linux_fs/kernel/Documentation/translations/zh_CN/arm64/
H A Dsilicon-errata.txt1 Chinese translated version of Documentation/arm64/silicon-errata.rst
4 original document maintainer directly. However, if you have a problem
7 or if there is a problem with the translation.
12 ---------------------------------------------------------------------
13 Documentation/arm64/silicon-errata.rst 的中文翻译
26 ---------------------------------------------------------------------
37 A 类：无可行补救措施的严重缺陷。
46 情况下，为将 A 类缺陷当作 C 类处理，可能需要用类似的手段。这些手段被
51 相应的内核配置（Kconfig）选项被加在 “内核特性（Kernel Features）”->
62 +----------------+-----------------+-----------------+-------------------------+
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/OK3568_Linux_fs/kernel/arch/arm/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0
131 The ARM series is a line of low-power-consumption RISC chip designs
133 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
134 manufactured, but legacy ARM-based PC hardware remains popular in
135 Europe. There is an ARM Linux project with a web page at
155 size. This works well for buffers up to a few hundreds kilobytes, but
156 for larger buffers it just a waste of address space. Drivers which has
158 virtual space with just a few allocations.
162 specified order. The order is expressed as a power of two multiplied
244 Patch phys-to-virt and virt-to-phys translation functions at
[all …]
/OK3568_Linux_fs/yocto/poky/meta/conf/machine/include/arm/armv8-2a/
H A Dtune-cortexa76-cortexa55.inc2 # Tune Settings for big.LITTLE Cortex-A76 - Cortex-A55
4 DEFAULTTUNE ?= "cortexa76-cortexa55"
6 TUNEVALID[cortexa76-cortexa55] = "Enable big.LITTLE Cortex-A76.Cortex-A55 specific processor optimi…
7 MACHINEOVERRIDES =. "${@bb.utils.contains("TUNE_FEATURES", "cortexa76-cortexa55", "cortexa76-cortex…
8 …ARGS .= "${@bb.utils.contains("TUNE_FEATURES", "cortexa76-cortexa55", " -mcpu=cortex-a76.cortex-a5…
10 require conf/machine/include/arm/arch-armv8-2a.inc
12 AVAILTUNES += "cortexa76-cortexa55 cortexa76-cortexa55-cryp…
13 ARMPKGARCH:tune-cortexa76-cortexa55 = "cortexa76-cortexa55"
14 ARMPKGARCH:tune-cortexa76-cortexa55-crypto = "cortexa76-cortexa55-crypto"
15 TUNE_FEATURES:tune-cortexa76-cortexa55 = "${TUNE_FEATURES:tune-armv8-2a} cortexa76-cor…
[all …]
H A Dtune-cortexa75-cortexa55.inc2 # Tune Settings for big.LITTLE Cortex-A75 - Cortex-A55
4 DEFAULTTUNE ?= "cortexa75-cortexa55"
6 TUNEVALID[cortexa75-cortexa55] = "Enable big.LITTLE Cortex-A75.Cortex-A55 specific processor optimi…
7 MACHINEOVERRIDES =. "${@bb.utils.contains("TUNE_FEATURES", "cortexa75-cortexa55", "cortexa75-cortex…
8 …ARGS .= "${@bb.utils.contains("TUNE_FEATURES", "cortexa75-cortexa55", " -mcpu=cortex-a75.cortex-a5…
10 require conf/machine/include/arm/arch-armv8-2a.inc
12 AVAILTUNES += "cortexa75-cortexa55 cortexa75-cortexa55-cryp…
13 ARMPKGARCH:tune-cortexa75-cortexa55 = "cortexa75-cortexa55"
14 ARMPKGARCH:tune-cortexa75-cortexa55-crypto = "cortexa75-cortexa55-crypto"
15 TUNE_FEATURES:tune-cortexa75-cortexa55 = "${TUNE_FEATURES:tune-armv8-2a} cortexa75-cor…
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/mach-rockchip/
H A DKconfig18 The Rockchip PX30 is a ARM-based SoC with a quad-core Cortex-A35
19 including NEON and GPU, Mali-400 graphics, several DDR3 options
26 default "arch/arm/mach-rockchip/u-boot-tpl-v8.lds"
55 The Rockchip RK3036 is a ARM-based SoC with a dual-core Cortex-A7
56 including NEON and GPU, Mali-400 graphics, several DDR3 options
66 The Rockchip RK3128 is a ARM-based SoC with a quad-core Cortex-A7
67 including NEON and GPU, Mali-400 graphics, several DDR3 options
83 PX3SE is a variant of RK3128, it shares codes with RK3128, but we still
98 The Rockchip RK3066 is a ARM-based SoC with a dual-core Cortex-A9
99 including NEON and GPU, Mali-400 graphics, several DDR3 options
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/timer/
H A Darm,twd.txt3 ARM 11MP, Cortex-A5 and Cortex-A9 are often associated with a per-core
4 Timer-Watchdog (aka TWD), which provides both a per-cpu local timer
7 The TWD is usually attached to a GIC to deliver its two per-processor
12 - compatible : Should be one of:
13 "arm,cortex-a9-twd-timer"
14 "arm,cortex-a5-twd-timer"
15 "arm,arm11mp-twd-timer"
17 - interrupts : One interrupt to each core
19 - reg : Specify the base address and the size of the TWD timer
24 - always-on : a boolean property. If present, the timer is powered through
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/cpu/armv8/fsl-layerscape/doc/
H A DREADME.soc11 ---------
12 The LS1043A integrated multicore processor combines four ARM Cortex-A53
18 - Four 64-bit ARM Cortex-A53 CPUs
19 - 1 MB unified L2 Cache
20 - One 32-bit DDR3L/DDR4 SDRAM memory controllers with ECC and interleaving
22 - Data Path Acceleration Architecture (DPAA) incorporating acceleration the
24 - Packet parsing, classification, and distribution (FMan)
25 - Queue management for scheduling, packet sequencing, and congestion
27 - Hardware buffer management for buffer allocation and de-allocation (BMan)
28 - Cryptography acceleration (SEC)
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/interrupt-controller/
H A Darm,gic.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/arm,gic.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Marc Zyngier <marc.zyngier@arm.com>
13 ARM SMP cores are often associated with a GIC, providing per processor
22 - $ref: /schemas/interrupt-controller.yaml#
27 - items:
28 - enum:
29 - arm,arm11mp-gic
[all …]

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