1*4882a593Smuzhiyun* ARM Snoop Control Unit (SCU) 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunAs part of the MPCore complex, Cortex-A5 and Cortex-A9 are provided 4*4882a593Smuzhiyunwith a Snoop Control Unit. The register range is usually 256 (0x100) 5*4882a593Smuzhiyunbytes. 6*4882a593Smuzhiyun 7*4882a593SmuzhiyunReferences: 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun- Cortex-A9: see DDI0407E Cortex-A9 MPCore Technical Reference Manual 10*4882a593Smuzhiyun Revision r2p0 11*4882a593Smuzhiyun- Cortex-A5: see DDI0434B Cortex-A5 MPCore Technical Reference Manual 12*4882a593Smuzhiyun Revision r0p1 13*4882a593Smuzhiyun- ARM11 MPCore: see DDI0360F ARM 11 MPCore Processor Technical Reference 14*4882a593Smuzhiyun Manial Revision r2p0 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun- compatible : Should be: 17*4882a593Smuzhiyun "arm,cortex-a9-scu" 18*4882a593Smuzhiyun "arm,cortex-a5-scu" 19*4882a593Smuzhiyun "arm,arm11mp-scu" 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun- reg : Specify the base address and the size of the SCU register window. 22*4882a593Smuzhiyun 23*4882a593SmuzhiyunExample: 24*4882a593Smuzhiyun 25*4882a593Smuzhiyunscu@a0410000 { 26*4882a593Smuzhiyun compatible = "arm,cortex-a9-scu"; 27*4882a593Smuzhiyun reg = <0xa0410000 0x100>; 28*4882a593Smuzhiyun}; 29