1<!DOCTYPE html PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd"> 2<html> 3<!-- This file documents the GNU Assembler "as". 4 5Copyright (C) 1991-2021 Free Software Foundation, Inc. 6 7Permission is granted to copy, distribute and/or modify this document 8under the terms of the GNU Free Documentation License, Version 1.3 9or any later version published by the Free Software Foundation; 10with no Invariant Sections, with no Front-Cover Texts, and with no 11Back-Cover Texts. A copy of the license is included in the 12section entitled "GNU Free Documentation License". 13 --> 14<!-- Created by GNU Texinfo 5.1, http://www.gnu.org/software/texinfo/ --> 15<head> 16<title>Using as: ARM Options</title> 17 18<meta name="description" content="Using as: ARM Options"> 19<meta name="keywords" content="Using as: ARM Options"> 20<meta name="resource-type" content="document"> 21<meta name="distribution" content="global"> 22<meta name="Generator" content="makeinfo"> 23<meta http-equiv="Content-Type" content="text/html; charset=utf-8"> 24<link href="index.html#Top" rel="start" title="Top"> 25<link href="AS-Index.html#AS-Index" rel="index" title="AS Index"> 26<link href="index.html#SEC_Contents" rel="contents" title="Table of Contents"> 27<link href="ARM_002dDependent.html#ARM_002dDependent" rel="up" title="ARM-Dependent"> 28<link href="ARM-Syntax.html#ARM-Syntax" rel="next" title="ARM Syntax"> 29<link href="ARM_002dDependent.html#ARM_002dDependent" rel="previous" title="ARM-Dependent"> 30<style type="text/css"> 31<!-- 32a.summary-letter {text-decoration: none} 33blockquote.smallquotation {font-size: smaller} 34div.display {margin-left: 3.2em} 35div.example {margin-left: 3.2em} 36div.indentedblock {margin-left: 3.2em} 37div.lisp {margin-left: 3.2em} 38div.smalldisplay {margin-left: 3.2em} 39div.smallexample {margin-left: 3.2em} 40div.smallindentedblock {margin-left: 3.2em; font-size: smaller} 41div.smalllisp {margin-left: 3.2em} 42kbd {font-style:oblique} 43pre.display {font-family: inherit} 44pre.format {font-family: inherit} 45pre.menu-comment {font-family: serif} 46pre.menu-preformatted {font-family: serif} 47pre.smalldisplay {font-family: inherit; font-size: smaller} 48pre.smallexample {font-size: smaller} 49pre.smallformat {font-family: inherit; font-size: smaller} 50pre.smalllisp {font-size: smaller} 51span.nocodebreak {white-space:nowrap} 52span.nolinebreak {white-space:nowrap} 53span.roman {font-family:serif; font-weight:normal} 54span.sansserif {font-family:sans-serif; font-weight:normal} 55ul.no-bullet {list-style: none} 56--> 57</style> 58 59 60</head> 61 62<body lang="en" bgcolor="#FFFFFF" text="#000000" link="#0000FF" vlink="#800080" alink="#FF0000"> 63<a name="ARM-Options"></a> 64<div class="header"> 65<p> 66Next: <a href="ARM-Syntax.html#ARM-Syntax" accesskey="n" rel="next">ARM Syntax</a>, Up: <a href="ARM_002dDependent.html#ARM_002dDependent" accesskey="u" rel="up">ARM-Dependent</a> [<a href="index.html#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="AS-Index.html#AS-Index" title="Index" rel="index">Index</a>]</p> 67</div> 68<hr> 69<a name="Options-3"></a> 70<h4 class="subsection">9.4.1 Options</h4> 71<a name="index-ARM-options-_0028none_0029"></a> 72<a name="index-options-for-ARM-_0028none_0029"></a> 73 74<dl compact="compact"> 75<dd> 76<a name="index-_002dmcpu_003d-command_002dline-option_002c-ARM"></a> 77</dd> 78<dt><code>-mcpu=<var>processor</var>[+<var>extension</var>…]</code></dt> 79<dd><p>This option specifies the target processor. The assembler will issue an 80error message if an attempt is made to assemble an instruction which 81will not execute on the target processor. The following processor names are 82recognized: 83<code>arm1</code>, 84<code>arm2</code>, 85<code>arm250</code>, 86<code>arm3</code>, 87<code>arm6</code>, 88<code>arm60</code>, 89<code>arm600</code>, 90<code>arm610</code>, 91<code>arm620</code>, 92<code>arm7</code>, 93<code>arm7m</code>, 94<code>arm7d</code>, 95<code>arm7dm</code>, 96<code>arm7di</code>, 97<code>arm7dmi</code>, 98<code>arm70</code>, 99<code>arm700</code>, 100<code>arm700i</code>, 101<code>arm710</code>, 102<code>arm710t</code>, 103<code>arm720</code>, 104<code>arm720t</code>, 105<code>arm740t</code>, 106<code>arm710c</code>, 107<code>arm7100</code>, 108<code>arm7500</code>, 109<code>arm7500fe</code>, 110<code>arm7t</code>, 111<code>arm7tdmi</code>, 112<code>arm7tdmi-s</code>, 113<code>arm8</code>, 114<code>arm810</code>, 115<code>strongarm</code>, 116<code>strongarm1</code>, 117<code>strongarm110</code>, 118<code>strongarm1100</code>, 119<code>strongarm1110</code>, 120<code>arm9</code>, 121<code>arm920</code>, 122<code>arm920t</code>, 123<code>arm922t</code>, 124<code>arm940t</code>, 125<code>arm9tdmi</code>, 126<code>fa526</code> (Faraday FA526 processor), 127<code>fa626</code> (Faraday FA626 processor), 128<code>arm9e</code>, 129<code>arm926e</code>, 130<code>arm926ej-s</code>, 131<code>arm946e-r0</code>, 132<code>arm946e</code>, 133<code>arm946e-s</code>, 134<code>arm966e-r0</code>, 135<code>arm966e</code>, 136<code>arm966e-s</code>, 137<code>arm968e-s</code>, 138<code>arm10t</code>, 139<code>arm10tdmi</code>, 140<code>arm10e</code>, 141<code>arm1020</code>, 142<code>arm1020t</code>, 143<code>arm1020e</code>, 144<code>arm1022e</code>, 145<code>arm1026ej-s</code>, 146<code>fa606te</code> (Faraday FA606TE processor), 147<code>fa616te</code> (Faraday FA616TE processor), 148<code>fa626te</code> (Faraday FA626TE processor), 149<code>fmp626</code> (Faraday FMP626 processor), 150<code>fa726te</code> (Faraday FA726TE processor), 151<code>arm1136j-s</code>, 152<code>arm1136jf-s</code>, 153<code>arm1156t2-s</code>, 154<code>arm1156t2f-s</code>, 155<code>arm1176jz-s</code>, 156<code>arm1176jzf-s</code>, 157<code>mpcore</code>, 158<code>mpcorenovfp</code>, 159<code>cortex-a5</code>, 160<code>cortex-a7</code>, 161<code>cortex-a8</code>, 162<code>cortex-a9</code>, 163<code>cortex-a15</code>, 164<code>cortex-a17</code>, 165<code>cortex-a32</code>, 166<code>cortex-a35</code>, 167<code>cortex-a53</code>, 168<code>cortex-a55</code>, 169<code>cortex-a57</code>, 170<code>cortex-a72</code>, 171<code>cortex-a73</code>, 172<code>cortex-a75</code>, 173<code>cortex-a76</code>, 174<code>cortex-a76ae</code>, 175<code>cortex-a77</code>, 176<code>cortex-a78</code>, 177<code>cortex-a78ae</code>, 178<code>cortex-a78c</code>, 179<code>ares</code>, 180<code>cortex-r4</code>, 181<code>cortex-r4f</code>, 182<code>cortex-r5</code>, 183<code>cortex-r7</code>, 184<code>cortex-r8</code>, 185<code>cortex-r52</code>, 186<code>cortex-m35p</code>, 187<code>cortex-m33</code>, 188<code>cortex-m23</code>, 189<code>cortex-m7</code>, 190<code>cortex-m4</code>, 191<code>cortex-m3</code>, 192<code>cortex-m1</code>, 193<code>cortex-m0</code>, 194<code>cortex-m0plus</code>, 195<code>cortex-x1</code>, 196<code>exynos-m1</code>, 197<code>marvell-pj4</code>, 198<code>marvell-whitney</code>, 199<code>neoverse-n1</code>, 200<code>neoverse-n2</code>, 201<code>neoverse-v1</code>, 202<code>xgene1</code>, 203<code>xgene2</code>, 204<code>ep9312</code> (ARM920 with Cirrus Maverick coprocessor), 205<code>i80200</code> (Intel XScale processor) 206<code>iwmmxt</code> (Intel XScale processor with Wireless MMX technology coprocessor) 207and 208<code>xscale</code>. 209The special name <code>all</code> may be used to allow the 210assembler to accept instructions valid for any ARM processor. 211</p> 212<p>In addition to the basic instruction set, the assembler can be told to 213accept various extension mnemonics that extend the processor using the 214co-processor instruction space. For example, <code>-mcpu=arm920+maverick</code> 215is equivalent to specifying <code>-mcpu=ep9312</code>. 216</p> 217<p>Multiple extensions may be specified, separated by a <code>+</code>. The 218extensions should be specified in ascending alphabetical order. 219</p> 220<p>Some extensions may be restricted to particular architectures; this is 221documented in the list of extensions below. 222</p> 223<p>Extension mnemonics may also be removed from those the assembler accepts. 224This is done be prepending <code>no</code> to the option that adds the extension. 225Extensions that are removed should be listed after all extensions which have 226been added, again in ascending alphabetical order. For example, 227<code>-mcpu=ep9312+nomaverick</code> is equivalent to specifying <code>-mcpu=arm920</code>. 228</p> 229 230<p>The following extensions are currently supported: 231<code>bf16</code> (BFloat16 extensions for v8.6-A architecture), 232<code>i8mm</code> (Int8 Matrix Multiply extensions for v8.6-A architecture), 233<code>crc</code> 234<code>crypto</code> (Cryptography Extensions for v8-A architecture, implies <code>fp+simd</code>), 235<code>dotprod</code> (Dot Product Extensions for v8.2-A architecture, implies <code>fp+simd</code>), 236<code>fp</code> (Floating Point Extensions for v8-A architecture), 237<code>fp16</code> (FP16 Extensions for v8.2-A architecture, implies <code>fp</code>), 238<code>fp16fml</code> (FP16 Floating Point Multiplication Variant Extensions for v8.2-A architecture, implies <code>fp16</code>), 239<code>idiv</code> (Integer Divide Extensions for v7-A and v7-R architectures), 240<code>iwmmxt</code>, 241<code>iwmmxt2</code>, 242<code>xscale</code>, 243<code>maverick</code>, 244<code>mp</code> (Multiprocessing Extensions for v7-A and v7-R 245architectures), 246<code>os</code> (Operating System for v6M architecture), 247<code>predres</code> (Execution and Data Prediction Restriction Instruction for 248v8-A architectures, added by default from v8.5-A), 249<code>sb</code> (Speculation Barrier Instruction for v8-A architectures, added by 250default from v8.5-A), 251<code>sec</code> (Security Extensions for v6K and v7-A architectures), 252<code>simd</code> (Advanced SIMD Extensions for v8-A architecture, implies <code>fp</code>), 253<code>virt</code> (Virtualization Extensions for v7-A architecture, implies 254<code>idiv</code>), 255<code>pan</code> (Privileged Access Never Extensions for v8-A architecture), 256<code>ras</code> (Reliability, Availability and Serviceability extensions 257for v8-A architecture), 258<code>rdma</code> (ARMv8.1 Advanced SIMD extensions for v8-A architecture, implies 259<code>simd</code>) 260and 261<code>xscale</code>. 262</p> 263<a name="index-_002dmarch_003d-command_002dline-option_002c-ARM"></a> 264</dd> 265<dt><code>-march=<var>architecture</var>[+<var>extension</var>…]</code></dt> 266<dd><p>This option specifies the target architecture. The assembler will issue 267an error message if an attempt is made to assemble an instruction which 268will not execute on the target architecture. The following architecture 269names are recognized: 270<code>armv1</code>, 271<code>armv2</code>, 272<code>armv2a</code>, 273<code>armv2s</code>, 274<code>armv3</code>, 275<code>armv3m</code>, 276<code>armv4</code>, 277<code>armv4xm</code>, 278<code>armv4t</code>, 279<code>armv4txm</code>, 280<code>armv5</code>, 281<code>armv5t</code>, 282<code>armv5txm</code>, 283<code>armv5te</code>, 284<code>armv5texp</code>, 285<code>armv6</code>, 286<code>armv6j</code>, 287<code>armv6k</code>, 288<code>armv6z</code>, 289<code>armv6kz</code>, 290<code>armv6-m</code>, 291<code>armv6s-m</code>, 292<code>armv7</code>, 293<code>armv7-a</code>, 294<code>armv7ve</code>, 295<code>armv7-r</code>, 296<code>armv7-m</code>, 297<code>armv7e-m</code>, 298<code>armv8-a</code>, 299<code>armv8.1-a</code>, 300<code>armv8.2-a</code>, 301<code>armv8.3-a</code>, 302<code>armv8-r</code>, 303<code>armv8.4-a</code>, 304<code>armv8.5-a</code>, 305<code>armv8-m.base</code>, 306<code>armv8-m.main</code>, 307<code>armv8.1-m.main</code>, 308<code>armv8.6-a</code>, 309<code>iwmmxt</code>, 310<code>iwmmxt2</code> 311and 312<code>xscale</code>. 313If both <code>-mcpu</code> and 314<code>-march</code> are specified, the assembler will use 315the setting for <code>-mcpu</code>. 316</p> 317<p>The architecture option can be extended with a set extension options. These 318extensions are context sensitive, i.e. the same extension may mean different 319things when used with different architectures. When used together with a 320<code>-mfpu</code> option, the union of both feature enablement is taken. 321See their availability and meaning below: 322</p> 323<p>For <code>armv5te</code>, <code>armv5texp</code>, <code>armv5tej</code>, <code>armv6</code>, <code>armv6j</code>, <code>armv6k</code>, <code>armv6z</code>, <code>armv6kz</code>, <code>armv6zk</code>, <code>armv6t2</code>, <code>armv6kt2</code> and <code>armv6zt2</code>: 324</p> 325<p><code>+fp</code>: Enables VFPv2 instructions. 326<code>+nofp</code>: Disables all FPU instrunctions. 327</p> 328<p>For <code>armv7</code>: 329</p> 330<p><code>+fp</code>: Enables VFPv3 instructions with 16 double-word registers. 331<code>+nofp</code>: Disables all FPU instructions. 332</p> 333<p>For <code>armv7-a</code>: 334</p> 335<p><code>+fp</code>: Enables VFPv3 instructions with 16 double-word registers. 336<code>+vfpv3-d16</code>: Alias for <code>+fp</code>. 337<code>+vfpv3</code>: Enables VFPv3 instructions with 32 double-word registers. 338<code>+vfpv3-d16-fp16</code>: Enables VFPv3 with half precision floating-point 339conversion instructions and 16 double-word registers. 340<code>+vfpv3-fp16</code>: Enables VFPv3 with half precision floating-point conversion 341instructions and 32 double-word registers. 342<code>+vfpv4-d16</code>: Enables VFPv4 instructions with 16 double-word registers. 343<code>+vfpv4</code>: Enables VFPv4 instructions with 32 double-word registers. 344<code>+simd</code>: Enables VFPv3 and NEONv1 instructions with 32 double-word 345registers. 346<code>+neon</code>: Alias for <code>+simd</code>. 347<code>+neon-vfpv3</code>: Alias for <code>+simd</code>. 348<code>+neon-fp16</code>: Enables VFPv3, half precision floating-point conversion and 349NEONv1 instructions with 32 double-word registers. 350<code>+neon-vfpv4</code>: Enables VFPv4 and NEONv1 with Fused-MAC instructions and 32 351double-word registers. 352<code>+mp</code>: Enables Multiprocessing Extensions. 353<code>+sec</code>: Enables Security Extensions. 354<code>+nofp</code>: Disables all FPU and NEON instructions. 355<code>+nosimd</code>: Disables all NEON instructions. 356</p> 357<p>For <code>armv7ve</code>: 358</p> 359<p><code>+fp</code>: Enables VFPv4 instructions with 16 double-word registers. 360<code>+vfpv4-d16</code>: Alias for <code>+fp</code>. 361<code>+vfpv3-d16</code>: Enables VFPv3 instructions with 16 double-word registers. 362<code>+vfpv3</code>: Enables VFPv3 instructions with 32 double-word registers. 363<code>+vfpv3-d16-fp16</code>: Enables VFPv3 with half precision floating-point 364conversion instructions and 16 double-word registers. 365<code>+vfpv3-fp16</code>: Enables VFPv3 with half precision floating-point conversion 366instructions and 32 double-word registers. 367<code>+vfpv4</code>: Enables VFPv4 instructions with 32 double-word registers. 368<code>+simd</code>: Enables VFPv4 and NEONv1 with Fused-MAC instructions and 32 369double-word registers. 370<code>+neon-vfpv4</code>: Alias for <code>+simd</code>. 371<code>+neon</code>: Enables VFPv3 and NEONv1 instructions with 32 double-word 372registers. 373<code>+neon-vfpv3</code>: Alias for <code>+neon</code>. 374<code>+neon-fp16</code>: Enables VFPv3, half precision floating-point conversion and 375NEONv1 instructions with 32 double-word registers. 376double-word registers. 377<code>+nofp</code>: Disables all FPU and NEON instructions. 378<code>+nosimd</code>: Disables all NEON instructions. 379</p> 380<p>For <code>armv7-r</code>: 381</p> 382<p><code>+fp.sp</code>: Enables single-precision only VFPv3 instructions with 16 383double-word registers. 384<code>+vfpv3xd</code>: Alias for <code>+fp.sp</code>. 385<code>+fp</code>: Enables VFPv3 instructions with 16 double-word registers. 386<code>+vfpv3-d16</code>: Alias for <code>+fp</code>. 387<code>+vfpv3xd-fp16</code>: Enables single-precision only VFPv3 and half 388floating-point conversion instructions with 16 double-word registers. 389<code>+vfpv3-d16-fp16</code>: Enables VFPv3 and half precision floating-point 390conversion instructions with 16 double-word registers. 391<code>+idiv</code>: Enables integer division instructions in ARM mode. 392<code>+nofp</code>: Disables all FPU instructions. 393</p> 394<p>For <code>armv7e-m</code>: 395</p> 396<p><code>+fp</code>: Enables single-precision only VFPv4 instructions with 16 397double-word registers. 398<code>+vfpvf4-sp-d16</code>: Alias for <code>+fp</code>. 399<code>+fpv5</code>: Enables single-precision only VFPv5 instructions with 16 400double-word registers. 401<code>+fp.dp</code>: Enables VFPv5 instructions with 16 double-word registers. 402<code>+fpv5-d16"</code>: Alias for <code>+fp.dp</code>. 403<code>+nofp</code>: Disables all FPU instructions. 404</p> 405<p>For <code>armv8-m.main</code>: 406</p> 407<p><code>+dsp</code>: Enables DSP Extension. 408<code>+fp</code>: Enables single-precision only VFPv5 instructions with 16 409double-word registers. 410<code>+fp.dp</code>: Enables VFPv5 instructions with 16 double-word registers. 411<code>+cdecp0</code> (CDE extensions for v8-m architecture with coprocessor 0), 412<code>+cdecp1</code> (CDE extensions for v8-m architecture with coprocessor 1), 413<code>+cdecp2</code> (CDE extensions for v8-m architecture with coprocessor 2), 414<code>+cdecp3</code> (CDE extensions for v8-m architecture with coprocessor 3), 415<code>+cdecp4</code> (CDE extensions for v8-m architecture with coprocessor 4), 416<code>+cdecp5</code> (CDE extensions for v8-m architecture with coprocessor 5), 417<code>+cdecp6</code> (CDE extensions for v8-m architecture with coprocessor 6), 418<code>+cdecp7</code> (CDE extensions for v8-m architecture with coprocessor 7), 419<code>+nofp</code>: Disables all FPU instructions. 420<code>+nodsp</code>: Disables DSP Extension. 421</p> 422<p>For <code>armv8.1-m.main</code>: 423</p> 424<p><code>+dsp</code>: Enables DSP Extension. 425<code>+fp</code>: Enables single and half precision scalar Floating Point Extensions 426for Armv8.1-M Mainline with 16 double-word registers. 427<code>+fp.dp</code>: Enables double precision scalar Floating Point Extensions for 428Armv8.1-M Mainline, implies <code>+fp</code>. 429<code>+mve</code>: Enables integer only M-profile Vector Extension for 430Armv8.1-M Mainline, implies <code>+dsp</code>. 431<code>+mve.fp</code>: Enables Floating Point M-profile Vector Extension for 432Armv8.1-M Mainline, implies <code>+mve</code> and <code>+fp</code>. 433<code>+nofp</code>: Disables all FPU instructions. 434<code>+nodsp</code>: Disables DSP Extension. 435<code>+nomve</code>: Disables all M-profile Vector Extensions. 436</p> 437<p>For <code>armv8-a</code>: 438</p> 439<p><code>+crc</code>: Enables CRC32 Extension. 440<code>+simd</code>: Enables VFP and NEON for Armv8-A. 441<code>+crypto</code>: Enables Cryptography Extensions for Armv8-A, implies 442<code>+simd</code>. 443<code>+sb</code>: Enables Speculation Barrier Instruction for Armv8-A. 444<code>+predres</code>: Enables Execution and Data Prediction Restriction Instruction 445for Armv8-A. 446<code>+nofp</code>: Disables all FPU, NEON and Cryptography Extensions. 447<code>+nocrypto</code>: Disables Cryptography Extensions. 448</p> 449<p>For <code>armv8.1-a</code>: 450</p> 451<p><code>+simd</code>: Enables VFP and NEON for Armv8.1-A. 452<code>+crypto</code>: Enables Cryptography Extensions for Armv8-A, implies 453<code>+simd</code>. 454<code>+sb</code>: Enables Speculation Barrier Instruction for Armv8-A. 455<code>+predres</code>: Enables Execution and Data Prediction Restriction Instruction 456for Armv8-A. 457<code>+nofp</code>: Disables all FPU, NEON and Cryptography Extensions. 458<code>+nocrypto</code>: Disables Cryptography Extensions. 459</p> 460<p>For <code>armv8.2-a</code> and <code>armv8.3-a</code>: 461</p> 462<p><code>+simd</code>: Enables VFP and NEON for Armv8.1-A. 463<code>+fp16</code>: Enables FP16 Extension for Armv8.2-A, implies <code>+simd</code>. 464<code>+fp16fml</code>: Enables FP16 Floating Point Multiplication Variant Extensions 465for Armv8.2-A, implies <code>+fp16</code>. 466<code>+crypto</code>: Enables Cryptography Extensions for Armv8-A, implies 467<code>+simd</code>. 468<code>+dotprod</code>: Enables Dot Product Extensions for Armv8.2-A, implies 469<code>+simd</code>. 470<code>+sb</code>: Enables Speculation Barrier Instruction for Armv8-A. 471<code>+predres</code>: Enables Execution and Data Prediction Restriction Instruction 472for Armv8-A. 473<code>+nofp</code>: Disables all FPU, NEON, Cryptography and Dot Product Extensions. 474<code>+nocrypto</code>: Disables Cryptography Extensions. 475</p> 476<p>For <code>armv8.4-a</code>: 477</p> 478<p><code>+simd</code>: Enables VFP and NEON for Armv8.1-A and Dot Product Extensions for 479Armv8.2-A. 480<code>+fp16</code>: Enables FP16 Floating Point and Floating Point Multiplication 481Variant Extensions for Armv8.2-A, implies <code>+simd</code>. 482<code>+crypto</code>: Enables Cryptography Extensions for Armv8-A, implies 483<code>+simd</code>. 484<code>+sb</code>: Enables Speculation Barrier Instruction for Armv8-A. 485<code>+predres</code>: Enables Execution and Data Prediction Restriction Instruction 486for Armv8-A. 487<code>+nofp</code>: Disables all FPU, NEON, Cryptography and Dot Product Extensions. 488<code>+nocryptp</code>: Disables Cryptography Extensions. 489</p> 490<p>For <code>armv8.5-a</code>: 491</p> 492<p><code>+simd</code>: Enables VFP and NEON for Armv8.1-A and Dot Product Extensions for 493Armv8.2-A. 494<code>+fp16</code>: Enables FP16 Floating Point and Floating Point Multiplication 495Variant Extensions for Armv8.2-A, implies <code>+simd</code>. 496<code>+crypto</code>: Enables Cryptography Extensions for Armv8-A, implies 497<code>+simd</code>. 498<code>+nofp</code>: Disables all FPU, NEON, Cryptography and Dot Product Extensions. 499<code>+nocryptp</code>: Disables Cryptography Extensions. 500</p> 501 502<a name="index-_002dmfpu_003d-command_002dline-option_002c-ARM"></a> 503</dd> 504<dt><code>-mfpu=<var>floating-point-format</var></code></dt> 505<dd> 506<p>This option specifies the floating point format to assemble for. The 507assembler will issue an error message if an attempt is made to assemble 508an instruction which will not execute on the target floating point unit. 509The following format options are recognized: 510<code>softfpa</code>, 511<code>fpe</code>, 512<code>fpe2</code>, 513<code>fpe3</code>, 514<code>fpa</code>, 515<code>fpa10</code>, 516<code>fpa11</code>, 517<code>arm7500fe</code>, 518<code>softvfp</code>, 519<code>softvfp+vfp</code>, 520<code>vfp</code>, 521<code>vfp10</code>, 522<code>vfp10-r0</code>, 523<code>vfp9</code>, 524<code>vfpxd</code>, 525<code>vfpv2</code>, 526<code>vfpv3</code>, 527<code>vfpv3-fp16</code>, 528<code>vfpv3-d16</code>, 529<code>vfpv3-d16-fp16</code>, 530<code>vfpv3xd</code>, 531<code>vfpv3xd-d16</code>, 532<code>vfpv4</code>, 533<code>vfpv4-d16</code>, 534<code>fpv4-sp-d16</code>, 535<code>fpv5-sp-d16</code>, 536<code>fpv5-d16</code>, 537<code>fp-armv8</code>, 538<code>arm1020t</code>, 539<code>arm1020e</code>, 540<code>arm1136jf-s</code>, 541<code>maverick</code>, 542<code>neon</code>, 543<code>neon-vfpv3</code>, 544<code>neon-fp16</code>, 545<code>neon-vfpv4</code>, 546<code>neon-fp-armv8</code>, 547<code>crypto-neon-fp-armv8</code>, 548<code>neon-fp-armv8.1</code> 549and 550<code>crypto-neon-fp-armv8.1</code>. 551</p> 552<p>In addition to determining which instructions are assembled, this option 553also affects the way in which the <code>.double</code> assembler directive behaves 554when assembling little-endian code. 555</p> 556<p>The default is dependent on the processor selected. For Architecture 5 or 557later, the default is to assemble for VFP instructions; for earlier 558architectures the default is to assemble for FPA instructions. 559</p> 560<a name="index-_002dmfp16_002dformat_003d-command_002dline-option"></a> 561</dd> 562<dt><code>-mfp16-format=<var>format</var></code></dt> 563<dd><p>This option specifies the half-precision floating point format to use 564when assembling floating point numbers emitted by the <code>.float16</code> 565directive. 566The following format options are recognized: 567<code>ieee</code>, 568<code>alternative</code>. 569If <code>ieee</code> is specified then the IEEE 754-2008 half-precision floating 570point format is used, if <code>alternative</code> is specified then the Arm 571alternative half-precision format is used. If this option is set on the 572command line then the format is fixed and cannot be changed with 573the <code>float16_format</code> directive. If this value is not set then 574the IEEE 754-2008 format is used until the format is explicitly set with 575the <code>float16_format</code> directive. 576</p> 577<a name="index-_002dmthumb-command_002dline-option_002c-ARM"></a> 578</dd> 579<dt><code>-mthumb</code></dt> 580<dd><p>This option specifies that the assembler should start assembling Thumb 581instructions; that is, it should behave as though the file starts with a 582<code>.code 16</code> directive. 583</p> 584<a name="index-_002dmthumb_002dinterwork-command_002dline-option_002c-ARM"></a> 585</dd> 586<dt><code>-mthumb-interwork</code></dt> 587<dd><p>This option specifies that the output generated by the assembler should 588be marked as supporting interworking. It also affects the behaviour 589of the <code>ADR</code> and <code>ADRL</code> pseudo opcodes. 590</p> 591<a name="index-_002dmimplicit_002dit-command_002dline-option_002c-ARM"></a> 592</dd> 593<dt><code>-mimplicit-it=never</code></dt> 594<dt><code>-mimplicit-it=always</code></dt> 595<dt><code>-mimplicit-it=arm</code></dt> 596<dt><code>-mimplicit-it=thumb</code></dt> 597<dd><p>The <code>-mimplicit-it</code> option controls the behavior of the assembler when 598conditional instructions are not enclosed in IT blocks. 599There are four possible behaviors. 600If <code>never</code> is specified, such constructs cause a warning in ARM 601code and an error in Thumb-2 code. 602If <code>always</code> is specified, such constructs are accepted in both 603ARM and Thumb-2 code, where the IT instruction is added implicitly. 604If <code>arm</code> is specified, such constructs are accepted in ARM code 605and cause an error in Thumb-2 code. 606If <code>thumb</code> is specified, such constructs cause a warning in ARM 607code and are accepted in Thumb-2 code. If you omit this option, the 608behavior is equivalent to <code>-mimplicit-it=arm</code>. 609</p> 610<a name="index-_002dmapcs_002d26-command_002dline-option_002c-ARM"></a> 611<a name="index-_002dmapcs_002d32-command_002dline-option_002c-ARM"></a> 612</dd> 613<dt><code>-mapcs-26</code></dt> 614<dt><code>-mapcs-32</code></dt> 615<dd><p>These options specify that the output generated by the assembler should 616be marked as supporting the indicated version of the Arm Procedure. 617Calling Standard. 618</p> 619<a name="index-_002dmatpcs-command_002dline-option_002c-ARM"></a> 620</dd> 621<dt><code>-matpcs</code></dt> 622<dd><p>This option specifies that the output generated by the assembler should 623be marked as supporting the Arm/Thumb Procedure Calling Standard. If 624enabled this option will cause the assembler to create an empty 625debugging section in the object file called .arm.atpcs. Debuggers can 626use this to determine the ABI being used by. 627</p> 628<a name="index-_002dmapcs_002dfloat-command_002dline-option_002c-ARM"></a> 629</dd> 630<dt><code>-mapcs-float</code></dt> 631<dd><p>This indicates the floating point variant of the APCS should be 632used. In this variant floating point arguments are passed in FP 633registers rather than integer registers. 634</p> 635<a name="index-_002dmapcs_002dreentrant-command_002dline-option_002c-ARM"></a> 636</dd> 637<dt><code>-mapcs-reentrant</code></dt> 638<dd><p>This indicates that the reentrant variant of the APCS should be used. 639This variant supports position independent code. 640</p> 641<a name="index-_002dmfloat_002dabi_003d-command_002dline-option_002c-ARM"></a> 642</dd> 643<dt><code>-mfloat-abi=<var>abi</var></code></dt> 644<dd><p>This option specifies that the output generated by the assembler should be 645marked as using specified floating point ABI. 646The following values are recognized: 647<code>soft</code>, 648<code>softfp</code> 649and 650<code>hard</code>. 651</p> 652<a name="index-_002deabi_003d-command_002dline-option_002c-ARM"></a> 653</dd> 654<dt><code>-meabi=<var>ver</var></code></dt> 655<dd><p>This option specifies which EABI version the produced object files should 656conform to. 657The following values are recognized: 658<code>gnu</code>, 659<code>4</code> 660and 661<code>5</code>. 662</p> 663<a name="index-_002dEB-command_002dline-option_002c-ARM"></a> 664</dd> 665<dt><code>-EB</code></dt> 666<dd><p>This option specifies that the output generated by the assembler should 667be marked as being encoded for a big-endian processor. 668</p> 669<p>Note: If a program is being built for a system with big-endian data 670and little-endian instructions then it should be assembled with the 671<samp>-EB</samp> option, (all of it, code and data) and then linked with 672the <samp>--be8</samp> option. This will reverse the endianness of the 673instructions back to little-endian, but leave the data as big-endian. 674</p> 675<a name="index-_002dEL-command_002dline-option_002c-ARM"></a> 676</dd> 677<dt><code>-EL</code></dt> 678<dd><p>This option specifies that the output generated by the assembler should 679be marked as being encoded for a little-endian processor. 680</p> 681<a name="index-_002dk-command_002dline-option_002c-ARM"></a> 682<a name="index-PIC-code-generation-for-ARM"></a> 683</dd> 684<dt><code>-k</code></dt> 685<dd><p>This option specifies that the output of the assembler should be marked 686as position-independent code (PIC). 687</p> 688<a name="index-_002d_002dfix_002dv4bx-command_002dline-option_002c-ARM"></a> 689</dd> 690<dt><code>--fix-v4bx</code></dt> 691<dd><p>Allow <code>BX</code> instructions in ARMv4 code. This is intended for use with 692the linker option of the same name. 693</p> 694<a name="index-_002dmwarn_002ddeprecated-command_002dline-option_002c-ARM"></a> 695</dd> 696<dt><code>-mwarn-deprecated</code></dt> 697<dt><code>-mno-warn-deprecated</code></dt> 698<dd><p>Enable or disable warnings about using deprecated options or 699features. The default is to warn. 700</p> 701<a name="index-_002dmccs-command_002dline-option_002c-ARM"></a> 702</dd> 703<dt><code>-mccs</code></dt> 704<dd><p>Turns on CodeComposer Studio assembly syntax compatibility mode. 705</p> 706<a name="index-_002dmwarn_002dsyms-command_002dline-option_002c-ARM"></a> 707</dd> 708<dt><code>-mwarn-syms</code></dt> 709<dt><code>-mno-warn-syms</code></dt> 710<dd><p>Enable or disable warnings about symbols that match the names of ARM 711instructions. The default is to warn. 712</p> 713</dd> 714</dl> 715 716 717<hr> 718<div class="header"> 719<p> 720Next: <a href="ARM-Syntax.html#ARM-Syntax" accesskey="n" rel="next">ARM Syntax</a>, Up: <a href="ARM_002dDependent.html#ARM_002dDependent" accesskey="u" rel="up">ARM-Dependent</a> [<a href="index.html#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="AS-Index.html#AS-Index" title="Index" rel="index">Index</a>]</p> 721</div> 722 723 724 725</body> 726</html> 727