Lines Matching +full:cortex +full:- +full:a
1 # SPDX-License-Identifier: GPL-2.0
131 The ARM series is a line of low-power-consumption RISC chip designs
133 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
134 manufactured, but legacy ARM-based PC hardware remains popular in
135 Europe. There is an ARM Linux project with a web page at
155 size. This works well for buffers up to a few hundreds kilobytes, but
156 for larger buffers it just a waste of address space. Drivers which has
158 virtual space with just a few allocations.
162 specified order. The order is expressed as a power of two multiplied
244 Patch phys-to-virt and virt-to-phys translation functions at
248 This can only be used with non-XIP MMU kernels where the base
249 of physical memory is at a 16MB boundary.
252 this feature (eg, building a kernel for a single machine) and
294 bool "MMU-based Paged Memory Management Support"
297 Select if you want MMU-based virtualised addressing space
336 bool "ARMv7-M based platforms (Cortex-M0/M3/M4)"
349 bool "EBSA-110"
358 from Digital. It has limited hardware on-board, including an
359 Ethernet interface, two PCMCIA sockets, two serial ports and a
363 bool "EP93xx-based"
391 bool "IOP32x-based"
404 bool "IXP4xx-based"
440 bool "PXA2xx/PXA3xx-based"
477 On the Acorn Risc-PC, Linux can support the internal IDE disk and
478 CD-ROM interface, serial and parallel port, and the floppy drive.
481 bool "SA1100-based"
579 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
608 # This is sorted alphabetically by mach-* pathname. However, plat-*
610 # plat- suffix) or along side the corresponding mach-* source.
612 source "arch/arm/mach-actions/Kconfig"
614 source "arch/arm/mach-alpine/Kconfig"
616 source "arch/arm/mach-artpec/Kconfig"
618 source "arch/arm/mach-asm9260/Kconfig"
620 source "arch/arm/mach-aspeed/Kconfig"
622 source "arch/arm/mach-at91/Kconfig"
624 source "arch/arm/mach-axxia/Kconfig"
626 source "arch/arm/mach-bcm/Kconfig"
628 source "arch/arm/mach-berlin/Kconfig"
630 source "arch/arm/mach-clps711x/Kconfig"
632 source "arch/arm/mach-cns3xxx/Kconfig"
634 source "arch/arm/mach-davinci/Kconfig"
636 source "arch/arm/mach-digicolor/Kconfig"
638 source "arch/arm/mach-dove/Kconfig"
640 source "arch/arm/mach-ep93xx/Kconfig"
642 source "arch/arm/mach-exynos/Kconfig"
644 source "arch/arm/mach-footbridge/Kconfig"
646 source "arch/arm/mach-gemini/Kconfig"
648 source "arch/arm/mach-highbank/Kconfig"
650 source "arch/arm/mach-hisi/Kconfig"
652 source "arch/arm/mach-imx/Kconfig"
654 source "arch/arm/mach-integrator/Kconfig"
656 source "arch/arm/mach-iop32x/Kconfig"
658 source "arch/arm/mach-ixp4xx/Kconfig"
660 source "arch/arm/mach-keystone/Kconfig"
662 source "arch/arm/mach-lpc32xx/Kconfig"
664 source "arch/arm/mach-mediatek/Kconfig"
666 source "arch/arm/mach-meson/Kconfig"
668 source "arch/arm/mach-milbeaut/Kconfig"
670 source "arch/arm/mach-mmp/Kconfig"
672 source "arch/arm/mach-moxart/Kconfig"
674 source "arch/arm/mach-mstar/Kconfig"
676 source "arch/arm/mach-mv78xx0/Kconfig"
678 source "arch/arm/mach-mvebu/Kconfig"
680 source "arch/arm/mach-mxs/Kconfig"
682 source "arch/arm/mach-nomadik/Kconfig"
684 source "arch/arm/mach-npcm/Kconfig"
686 source "arch/arm/mach-nspire/Kconfig"
688 source "arch/arm/plat-omap/Kconfig"
690 source "arch/arm/mach-omap1/Kconfig"
692 source "arch/arm/mach-omap2/Kconfig"
694 source "arch/arm/mach-orion5x/Kconfig"
696 source "arch/arm/mach-oxnas/Kconfig"
698 source "arch/arm/mach-picoxcell/Kconfig"
700 source "arch/arm/mach-prima2/Kconfig"
702 source "arch/arm/mach-pxa/Kconfig"
703 source "arch/arm/plat-pxa/Kconfig"
705 source "arch/arm/mach-qcom/Kconfig"
707 source "arch/arm/mach-rda/Kconfig"
709 source "arch/arm/mach-realtek/Kconfig"
711 source "arch/arm/mach-realview/Kconfig"
713 source "arch/arm/mach-rockchip/Kconfig"
715 source "arch/arm/mach-s3c/Kconfig"
717 source "arch/arm/mach-s5pv210/Kconfig"
719 source "arch/arm/mach-sa1100/Kconfig"
721 source "arch/arm/mach-shmobile/Kconfig"
723 source "arch/arm/mach-socfpga/Kconfig"
725 source "arch/arm/mach-spear/Kconfig"
727 source "arch/arm/mach-sti/Kconfig"
729 source "arch/arm/mach-stm32/Kconfig"
731 source "arch/arm/mach-sunxi/Kconfig"
733 source "arch/arm/mach-tango/Kconfig"
735 source "arch/arm/mach-tegra/Kconfig"
737 source "arch/arm/mach-u300/Kconfig"
739 source "arch/arm/mach-uniphier/Kconfig"
741 source "arch/arm/mach-ux500/Kconfig"
743 source "arch/arm/mach-versatile/Kconfig"
745 source "arch/arm/mach-vexpress/Kconfig"
747 source "arch/arm/mach-vt8500/Kconfig"
749 source "arch/arm/mach-zx/Kconfig"
751 source "arch/arm/mach-zynq/Kconfig"
753 # ARMv7-M architecture
770 Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4
779 Support for Cortex-M Prototyping System (or V2M-MPS2) which comes
780 with a range of available cores like Cortex-M3/M4/M7.
818 running on a CPU that supports it.
821 source "arch/arm/Kconfig-nommu"
829 When coming out of either a Wait for Interrupt (WFI) or a Wait for
830 Event (WFE) IDLE states, a specific timing sensitivity exists between
832 instructions. This sensitivity can result in a CPU hang scenario.
834 The software must insert either a Data Synchronization Barrier (DSB)
839 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
842 Executing a SWP instruction to read-only memory does not set bit 11
844 treat the access as a read, preventing a COW from occurring and
860 This option enables the workaround for the 430973 Cortex-A8
861 r1p* erratum. If a code sequence containing an ARM/Thumb
863 same virtual address, whether due to self-modifying code or virtual
864 to physical address re-mapping, Cortex-A8 does not recover from the
865 stale interworking branch prediction. This results in Cortex-A8
870 available in non-secure mode.
873 bool "ARM errata: Processor deadlock when a false hazard is created"
877 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
879 possible for a hazard condition intended for a cache line to instead
880 be incorrectly associated with a different cache line. This false
881 hazard might then cause a processor deadlock. The workaround enables
884 register may not be available in non-secure mode.
891 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
892 erratum. Any asynchronous access to the L2 cache may encounter a
895 workaround disables the write-allocate mode for the L2 cache via the
897 may not be available in non-secure mode.
904 This option enables the workaround for the 742230 Cortex-A9
905 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
907 ordering of the two writes. This workaround sets a specific bit in
908 the diagnostic register of the Cortex-A9 which causes the DMB
909 instruction to behave as a DSB, ensuring the correct behaviour of
917 This option enables the workaround for the 742231 Cortex-A9
919 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
924 register of the Cortex-A9 which reduces the linefill issuing
932 This option enables the workaround for the 643719 Cortex-A9 (prior to
939 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
942 This option enables the workaround for the 720789 Cortex-A9 (prior to
943 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
945 As a consequence of this erratum, some TLB entries which should be
955 This option enables the workaround for the 743622 Cortex-A9
956 (r2p*) erratum. Under very rare conditions, a faulty
957 optimisation in the Cortex-A9 Store Buffer may lead to data
958 corruption. This workaround sets a specific bit in the diagnostic
959 register of the Cortex-A9 which disables the Store Buffer
969 This option enables the workaround for the 751472 Cortex-A9 (prior
971 completion of a following broadcasted operation if the second
972 operation is received by a CPU before the ICIALLUIS has completed,
979 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
980 r3p*) erratum. A speculative memory access may cause a page table walk
982 can populate the micro-TLB with a stale entry which may be hit with
990 This option enables the workaround for the 754327 Cortex-A9 (prior to
992 mechanism and therefore a livelock may occur if an external agent
993 continuously polls a memory location waiting to observe an update.
998 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1003 hit-under-miss enabled). It sets the undocumented bit 31 in
1005 register, thus disabling hit-under-miss without putting the
1014 affecting Cortex-A9 MPCore with two or more processors (all
1015 current revisions). Under certain timing circumstances, a data
1019 system. This workaround adds a DSB instruction before the
1020 relevant cache maintenance functions and sets a specific bit
1024 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1027 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1028 r2p6,r2p8,r2p10,r3p0) erratum. In case a data cache maintenance
1034 bool "ARM errata: TLBI/DSB failure on Cortex-A15"
1037 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
1047 This option enables the workaround for the 773022 Cortex-A15
1057 - Cortex-A12 818325: Execution of an UNPREDICTABLE STR or STM
1059 - Cortex-A12 852422: Execution of a sequence of instructions might
1060 lead to either a data corruption or a CPU deadlock. Not fixed in
1061 any Cortex-A12 cores yet.
1063 Feature Register. This bit disables an optimisation applied to a
1067 bool "ARM errata: A12: sequence of VMOV to core registers might lead to a dead lock"
1070 This option enables the workaround for the 821420 Cortex-A12
1071 (all revs) erratum. In very rare timing conditions, a sequence
1073 one is in the shadow of a branch or abort, can lead to a
1074 deadlock when the VMOV instructions are issued out-of-order.
1080 This option enables the workaround for the 825619 Cortex-A12
1081 (all revs) erratum. Within rare timing constraints, executing a
1082 DMB NSHST or DMB ISHST instruction followed by a mix of Cacheable
1083 and Device/Strongly-Ordered loads and stores might cause deadlock
1089 This option enables the workaround for the 857271 Cortex-A12
1091 hang. The workaround is expected to have a < 1% performance impact.
1097 This option enables the workaround for the 852421 Cortex-A17
1099 execution of a DMB ST instruction might fail to properly order
1107 - Cortex-A17 852423: Execution of a sequence of instructions might
1108 lead to either a data corruption or a CPU deadlock. Not fixed in
1109 any Cortex-A17 cores yet.
1110 This is identical to Cortex-A12 erratum 852422. It is a separate
1118 This option enables the workaround for the 857272 Cortex-A17 erratum.
1120 This is identical to Cortex-A12 erratum 857271. It is a separate
1134 name of a bus system, i.e. the way the CPU talks to the other stuff
1163 This ERRATA only affected the Cortex-A7 and present in r0p2, r0p3,
1173 This option should be selected by machines which have an SMP-
1176 The only effect of this option is to make the SMP-related
1180 bool "Symmetric Multi-Processing"
1188 a system with only one CPU, say N. If you have a system with more
1191 If you say N here, the kernel will run on uni- and multiprocessor
1192 machines, but will use only one CPU of a multiprocessor machine. If
1194 uniprocessor machines. On a uniprocessor machine, the kernel
1197 See also <file:Documentation/x86/i386/IO-APIC.rst>,
1198 <file:Documentation/admin-guide/lockup-watchdogs.rst> and the SMP-HOWTO available at
1199 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1208 SMP kernels contain instructions which fail on non-SMP processors.
1225 bool "Multi-core scheduler support"
1228 Multi-core scheduler support improves the CPU scheduler's decision
1229 making when dealing with multi-core CPU chips at a cost of slightly
1237 MultiThreading at a cost of slightly increased overhead in some
1258 bool "Multi-Cluster Power Management"
1262 for (multi-)cluster based systems, such as big.LITTLE based
1288 transparently handle transition between a cluster of A15's
1289 and a cluster of A7's in a big.LITTLE system.
1295 This is a simple and dummy char dev interface to control
1329 int "Maximum number of CPUs (2-32)"
1335 bool "Support for hot-pluggable CPUs"
1348 implementing the PSCI specification for CPU-centric power
1350 0022A ("Power State Coordination Interface System Software on
1354 # a multiplatform kernel, we just want the highest value required by the
1418 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1424 Thumb-2 mode.
1452 ARM ABI (aka EABI). This is only useful if you are using a user
1468 new (ARM EABI) one. It also provides a compatibility layer to
1471 (only for non "thumb" binaries). This option adds a tiny
1472 overhead to all syscalls and produces a slightly larger kernel.
1480 to execute a legacy ABI binary then the result will be
1504 have a large amount of physical memory and/or IO, not all of the
1510 option which should result in a slightly faster kernel.
1515 bool "Allocate 2nd-level pagetables from highmem" if EXPERT
1520 For systems with a lot of processes, this can use a lot of
1523 user-space 2nd level page tables to reside in high memory.
1526 bool "Enable use of CPU domains to implement privileged no-access"
1532 use-after-free bugs becoming an exploitable privilege escalation
1536 CPUs with low-vector mappings use a best-efforts implementation.
1569 Disabling this is usually safe for small single-platform
1579 blocks into "zones", where each zone is a power of two number of
1586 a value of 11 means that the largest free memory block is 2^10 pages.
1595 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1596 address divisible by 4. On 32-bit ARM processors, these non-aligned
1598 here, which has a severe performance impact. This is necessary for
1599 correct operation of some network protocols. With an IP-only
1608 cores where a 8-word STM instruction give significantly higher
1609 memory write throughput than a sequence of individual 32bit stores.
1611 A possible side effect is a slight increase in scheduling latency
1615 However, if the CPU data cache is using a write-allocate mode,
1622 under a hypervisor, potentially improving performance significantly
1632 that, there can be a small performance impact.
1652 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1655 bool "Use a unique stack canary value for each task"
1666 Enable this option to switch to a different method that uses a
1703 The physical address at which the ROM-able zImage is to be
1705 ROM-able zImage formats normally set this to a suitable
1715 for the ROM-able zImage which must be available while the
1718 Platforms which normally make use of ROM-able zImage formats
1719 normally set this to a suitable value in their defconfig file.
1735 With this option, the boot code will look for a device tree binary
1739 This is meant as a backward compatibility convenience for those
1740 systems with a bootloader that can't be upgraded to accommodate
1741 the documented boot protocol using a device tree.
1745 look like a DTB header after a reboot if no actual DTB is appended
1746 to zImage. Do not leave this option active in a production kernel
1747 if you don't intend to always append a DTB. Proper passing of the
1748 location into r2 of a bootloader provided DTB is always preferable
1755 Some old bootloaders can't be updated to a DTB capable one, yet
1758 provided by the bootloader and can't always be stored in a static
1759 DTB. To allow a device tree enabled kernel to be used with such
1770 Uses the command-line options passed by the boot loader instead of
1777 The command-line arguments provided by the boot loader will be
1788 architectures, you should supply some command-line options at build
1789 time by entering them here. As a minimum, you should specify the
1799 Uses the command-line options passed by the boot loader. If
1806 The command-line arguments provided by the boot loader will be
1815 command-line options your boot loader passes to the kernel.
1819 bool "Kernel Execute-In-Place from ROM"
1822 Execute-In-Place allows the kernel to run from non-volatile storage
1825 to RAM. Read-write sections, such as the data section and stack,
1856 copied, saving some precious ROM space. A possible drawback is a
1865 kexec is a system call that implements the ability to shutdown your
1866 current kernel, and to start another kernel. It is like a reboot
1867 but it is independent of the system firmware. And like a reboot
1870 It is an ongoing process to be certain the hardware in a machine
1887 loaded in the main kernel with kexec-tools into a specially
1888 reserved region and then later executed after a crash by
1889 kdump/kexec. The crash dump kernel must be compiled to a
1892 For more details see Documentation/admin-guide/kdump/kdump.rst
1899 will be determined at run-time by masking the current IP with
1916 by UEFI firmware (such as non-volatile variables, realtime
1917 clock, and platform reset). A UEFI stub is also provided to
1931 continue to boot on existing non-UEFI platforms.
1937 to be enabled much earlier than we do on ARM, which is non-trivial.
1960 your machine has an FPA or floating point co-processor podule.
1969 Say Y to include 80-bit support in the kernel floating-point
1970 emulator. Otherwise, only 32 and 64-bit support is compiled in.
1971 Note that gcc does not generate 80-bit operations by default,
1984 It is very simple, and approximately 3-6 times faster than NWFPE.
1988 If you do not feel you need a faster FP emulation you should better
1992 bool "VFP-format floating point maths"
1996 if your hardware includes a VFP unit.
1998 Please see <file:Documentation/arm/vfp/release-notes.rst> for