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/OK3568_Linux_fs/kernel/drivers/hwtracing/coresight/
H A DMakefile3 # Makefile for CoreSight drivers.
5 obj-$(CONFIG_CORESIGHT) += coresight.o
6 coresight-y := coresight-core.o coresight-etm-perf.o coresight-platform.o \
7 coresight-sysfs.o
8 obj-$(CONFIG_CORESIGHT_LINK_AND_SINK_TMC) += coresight-tmc.o
9 coresight-tmc-y := coresight-tmc-core.o coresight-tmc-etf.o \
10 coresight-tmc-etr.o
11 obj-$(CONFIG_CORESIGHT_SINK_TPIU) += coresight-tpiu.o
12 obj-$(CONFIG_CORESIGHT_SINK_ETBV10) += coresight-etb10.o
13 obj-$(CONFIG_CORESIGHT_LINKS_AND_SINKS) += coresight-funnel.o \
[all …]
H A DKconfig3 # Coresight configuration
5 menuconfig CORESIGHT config
6 tristate "CoreSight Tracing Support"
12 This framework provides a kernel interface for the CoreSight debug
14 a topological view of the CoreSight components based on a DT
19 module will be called coresight.
21 if CORESIGHT
23 tristate "CoreSight Link and Sink drivers"
25 This enables support for CoreSight link and sink drivers that are
31 modules will be called coresight-funnel and coresight-replicator.
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/OK3568_Linux_fs/kernel/Documentation/ABI/testing/
H A Dsysfs-device-mali-coresight-source16 What: /sys/bus/coresight/devices/mali-source-etm/enable_source
18 Attribute used to enable Coresight Source ETM.
20 What: /sys/bus/coresight/devices/mali-source-etm/is_enabled
22 Attribute used to check if Coresight Source ITM is enabled.
24 What: /sys/bus/coresight/devices/mali-source-etm/trcconfigr
26 Coresight Source ETM trace configuration to enable global
29 What: /sys/bus/coresight/devices/mali-source-etm/trctraceidr
31 Coresight Source ETM trace ID.
33 What: /sys/bus/coresight/devices/mali-source-etm/trcvdarcctlr
35 Coresight Source ETM viewData include/exclude address
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H A Dsysfs-bus-coresight-devices-etm4x1 What: /sys/bus/coresight/devices/etm<N>/enable_source
8 of coresight components linking the source to the sink is
9 configured and managed automatically by the coresight framework.
11 What: /sys/bus/coresight/devices/etm<N>/cpu
17 What: /sys/bus/coresight/devices/etm<N>/nr_pe_cmp
24 What: /sys/bus/coresight/devices/etm<N>/nr_addr_cmp
31 What: /sys/bus/coresight/devices/etm<N>/nr_cntr
38 What: /sys/bus/coresight/devices/etm<N>/nr_ext_inp
44 What: /sys/bus/coresight/devices/etm<N>/numcidc
51 What: /sys/bus/coresight/devices/etm<N>/numvmidc
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H A Dsysfs-bus-coresight-devices-cti1 What: /sys/bus/coresight/devices/<cti-name>/enable
7 What: /sys/bus/coresight/devices/<cti-name>/powered
13 What: /sys/bus/coresight/devices/<cti-name>/ctmid
19 What: /sys/bus/coresight/devices/<cti-name>/nr_trigger_cons
25 What: /sys/bus/coresight/devices/<cti-name>/triggers<N>/name
31 What: /sys/bus/coresight/devices/<cti-name>/triggers<N>/in_signals
37 What: /sys/bus/coresight/devices/<cti-name>/triggers<N>/in_types
44 What: /sys/bus/coresight/devices/<cti-name>/triggers<N>/out_signals
50 What: /sys/bus/coresight/devices/<cti-name>/triggers<N>/out_types
57 What: /sys/bus/coresight/devices/<cti-name>/regs/inout_sel
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H A Dsysfs-bus-coresight-devices-etm3x1 What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/enable_source
8 of coresight components linking the source to the sink is
9 configured and managed automatically by the coresight framework.
11 What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/addr_idx
18 What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/addr_acctype
29 What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/addr_range
37 What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/addr_single
45 What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/addr_start
53 What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/addr_stop
61 What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/cntr_idx
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H A Dsysfs-bus-coresight-devices-tmc1 What: /sys/bus/coresight/devices/<memory_map>.tmc/trigger_cntr
10 What: /sys/bus/coresight/devices/<memory_map>.tmc/mgmt/rsz
17 What: /sys/bus/coresight/devices/<memory_map>.tmc/mgmt/sts
24 What: /sys/bus/coresight/devices/<memory_map>.tmc/mgmt/rrp
33 What: /sys/bus/coresight/devices/<memory_map>.tmc/mgmt/rwp
39 the CoreSight bus into the Trace RAM. The value is read directly
42 What: /sys/bus/coresight/devices/<memory_map>.tmc/mgmt/trg
49 What: /sys/bus/coresight/devices/<memory_map>.tmc/mgmt/ctl
56 What: /sys/bus/coresight/devices/<memory_map>.tmc/mgmt/ffsr
64 What: /sys/bus/coresight/devices/<memory_map>.tmc/mgmt/ffcr
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H A Dsysfs-bus-coresight-devices-etb101 What: /sys/bus/coresight/devices/<memory_map>.etb/enable_sink
10 echo 1 > /sys/bus/coresight/devices/20010000.etb/enable_sink
12 What: /sys/bus/coresight/devices/<memory_map>.etb/trigger_cntr
22 What: /sys/bus/coresight/devices/<memory_map>.etb/mgmt/rdp
29 What: /sys/bus/coresight/devices/<memory_map>.etb/mgmt/sts
36 What: /sys/bus/coresight/devices/<memory_map>.etb/mgmt/rrp
45 What: /sys/bus/coresight/devices/<memory_map>.etb/mgmt/rwp
51 the CoreSight bus into the Trace RAM. The value is read directly
54 What: /sys/bus/coresight/devices/<memory_map>.etb/mgmt/trg
61 What: /sys/bus/coresight/devices/<memory_map>.etb/mgmt/ctl
[all …]
H A Dsysfs-bus-coresight-devices-stm1 What: /sys/bus/coresight/devices/<memory_map>.stm/enable_source
8 of coresight components linking the source to the sink is
9 configured and managed automatically by the coresight framework.
11 What: /sys/bus/coresight/devices/<memory_map>.stm/hwevent_enable
18 What: /sys/bus/coresight/devices/<memory_map>.stm/hwevent_select
26 What: /sys/bus/coresight/devices/<memory_map>.stm/port_enable
34 What: /sys/bus/coresight/devices/<memory_map>.stm/port_select
41 What: /sys/bus/coresight/devices/<memory_map>.stm/status
48 What: /sys/bus/coresight/devices/<memory_map>.stm/traceid
/OK3568_Linux_fs/kernel/drivers/gpu/arm/bifrost/debug/backend/
H A Dmali_kbase_debug_coresight_csf.c235 dev_dbg(kbdev->dev, "Coresight config (0x%pK) state transition: %s to %s", config, in coresight_config_enable()
265 dev_dbg(kbdev->dev, "Coresight config (0x%pK) state transition: %s to %s", config, in coresight_config_disable()
319 spin_lock_irqsave(&kbdev->csf.coresight.lock, flags); in kbase_debug_coresight_csf_register()
320 list_for_each_entry(client_entry, &kbdev->csf.coresight.clients, link) { in kbase_debug_coresight_csf_register()
331 spin_unlock_irqrestore(&kbdev->csf.coresight.lock, flags); in kbase_debug_coresight_csf_register()
347 list_add(&client->link, &kbdev->csf.coresight.clients); in kbase_debug_coresight_csf_register()
348 spin_unlock_irqrestore(&kbdev->csf.coresight.lock, flags); in kbase_debug_coresight_csf_register()
376 spin_lock_irqsave(&kbdev->csf.coresight.lock, flags); in kbase_debug_coresight_csf_unregister()
379 while (retry && !list_empty(&kbdev->csf.coresight.configs)) { in kbase_debug_coresight_csf_unregister()
381 list_for_each_entry(config_entry, &kbdev->csf.coresight.configs, link) { in kbase_debug_coresight_csf_unregister()
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H A Dmali_kbase_debug_coresight_internal_csf.h29 * struct kbase_debug_coresight_csf_client - Coresight client definition
34 * @link: Link item of a Coresight client.
35 * Linked to &struct_kbase_device.csf.coresight.clients.
45 * enum kbase_debug_coresight_csf_state - Coresight configuration states
47 * @KBASE_DEBUG_CORESIGHT_CSF_DISABLED: Coresight configuration is disabled.
48 * @KBASE_DEBUG_CORESIGHT_CSF_ENABLED: Coresight configuration is enabled.
56 * struct kbase_debug_coresight_csf_config - Coresight configuration definition
59 * @enable_seq: Array of operations for Coresight client enable sequence. Can be NULL.
60 * @disable_seq: Array of operations for Coresight client disable sequence. Can be NULL.
61 * @state: Current Coresight configuration state.
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/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/arm/
H A Dcoresight.txt1 * CoreSight Components:
3 CoreSight components are compliant with the ARM CoreSight architecture
8 sink. Each CoreSight component device should use these properties to describe
17 "arm,coresight-etb10", "arm,primecell";
20 "arm,coresight-tpiu", "arm,primecell";
26 "arm,coresight-tmc", "arm,primecell";
29 "arm,coresight-dynamic-funnel", "arm,primecell";
30 "arm,coresight-funnel", "arm,primecell"; (OBSOLETE. For
35 "arm,coresight-etm3x", "arm,primecell";
38 "arm,coresight-etm4x", "arm,primecell";
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H A Dcoresight-cti.yaml5 $id: http://devicetree.org/schemas/arm/coresight-cti.yaml#
8 title: ARM Coresight Cross Trigger Interface (CTI) device.
11 The CoreSight Embedded Cross Trigger (ECT) consists of CTI devices connected
12 to one or more CoreSight components and/or a CPU, with CTIs interconnected in
15 not part of the CoreSight graph described in the general CoreSight bindings
16 file coresight.txt.
38 indicate this feature (arm,coresight-cti-v8-arch).
49 between CTI and other CoreSight components.
51 Certain triggers between CoreSight devices and the CTI have specific types
53 constants defined in <dt-bindings/arm/coresight-cti-dt.h>
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H A Dmali-coresight-source.txt21 ARM CoreSight Mali Source integration
24 See Documentation/trace/coresight/coresight.rst for detailed information
25 about Coresight.
32 ARM Coresight Mali Source ITM
38 - compatible: Has to be "arm,coresight-mali-source-itm"
42 - remote-endpoint: phandle to a Coresight sink port
48 compatible = "arm,coresight-mali-source-itm";
57 ARM Coresight Mali Source ETM
63 - compatible: Has to be "arm,coresight-mali-source-etm"
67 - remote-endpoint: phandle to a Coresight sink port
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H A Dete.yaml16 allows tracing the CPU execution. It overlaps with the CoreSight ETMv4
18 The trace generated by the ETE could be stored via legacy CoreSight
21 legacy CoreSight components, a node must be listed per instance, along
22 with any optional connection graph as per the coresight bindings.
23 See bindings/arm/coresight.txt.
39 Output connections from the ETE to legacy CoreSight trace bus.
43 description: Output connection from the ETE to legacy CoreSight Trace bus.
54 # An ETE node without legacy CoreSight connections
60 # An ETE node with legacy CoreSight connections
66 out-ports { /* legacy coresight connection */
/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/hisilicon/
H A Dhi6220-coresight.dtsi3 * dtsi file for Hisilicon Hi6220 coresight
14 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
39 compatible = "arm,coresight-tmc", "arm,primecell";
64 compatible = "arm,coresight-static-replicator";
100 compatible = "arm,coresight-tmc", "arm,primecell";
116 compatible = "arm,coresight-tpiu", "arm,primecell";
132 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
217 compatible = "arm,coresight-etm4x", "arm,primecell";
236 compatible = "arm,coresight-etm4x", "arm,primecell";
255 compatible = "arm,coresight-etm4x", "arm,primecell";
[all …]
H A Dhi3660-coresight.dtsi4 * dtsi for Hisilicon Hi3660 Coresight
15 compatible = "arm,coresight-etm4x", "arm,primecell";
32 compatible = "arm,coresight-etm4x", "arm,primecell";
49 compatible = "arm,coresight-etm4x", "arm,primecell";
66 compatible = "arm,coresight-etm4x", "arm,primecell";
83 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
132 compatible = "arm,coresight-tmc", "arm,primecell";
158 compatible = "arm,coresight-etm4x", "arm,primecell";
175 compatible = "arm,coresight-etm4x", "arm,primecell";
192 compatible = "arm,coresight-etm4x", "arm,primecell";
[all …]
/OK3568_Linux_fs/kernel/include/linux/
H A Dmali_kbase_debug_coresight_csf.h40 * struct kbase_debug_coresight_csf_write_imm_op - Coresight immediate write operation structure
51 * struct kbase_debug_coresight_csf_write_imm_range_op - Coresight immediate write range
65 * struct kbase_debug_coresight_csf_write_op - Coresight write operation structure
76 * struct kbase_debug_coresight_csf_read_op - Coresight read operation structure
87 * struct kbase_debug_coresight_csf_poll_op - Coresight poll operation structure
100 * struct kbase_debug_coresight_csf_bitw_op - Coresight bitwise operation structure
111 * struct kbase_debug_coresight_csf_op - Coresight supported operations
141 * struct kbase_debug_coresight_csf_sequence - Coresight sequence of operations
143 * @ops: Arrays containing Coresight operations.
152 * struct kbase_debug_coresight_csf_address_range - Coresight client address range
[all …]
/OK3568_Linux_fs/kernel/Documentation/trace/coresight/
H A Dcoresight.rst2 Coresight - HW Assisted Tracing on ARM
11 Coresight is an umbrella of technologies allowing for the debugging of ARM
24 flows through the coresight system (via ATB bus) using links that are connecting
25 the emanating source to a sink(s). Sinks serve as endpoints to the coresight
28 host without fear of filling up the onboard coresight memory buffer.
30 At typical coresight system would look like this::
85 a way to aggregate and distribute signals between CoreSight components.
87 The coresight framework provides a central point to represent, configure and
88 manage coresight devices on a platform. This first implementation centers on
133 See Documentation/devicetree/bindings/arm/coresight.txt for details.
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H A Dcoresight-trbe.rst15 gets plugged in as a coresight sink device because the corresponding trace
18 The TRBE is not compliant to CoreSight architecture specifications, but is
19 driven via the CoreSight driver framework to support the ETE (which is
20 CoreSight compliant) integration.
25 The TRBE devices appear on the existing coresight bus alongside the other
26 coresight devices::
28 >$ ls /sys/bus/coresight/devices
33 >$ ls /sys/bus/coresight/devices/trbe0/
H A Dcoresight-cpu-debug.rst2 Coresight CPU Debug Module
11 Coresight CPU debug module is defined in ARMv8-a architecture reference manual
107 power down in the way that the CoreSight / Debug designers anticipated.
120 See Documentation/devicetree/bindings/arm/coresight-cpu-debug.txt for details.
183 coresight-cpu-debug 850000.debug: CPU[0]:
184 coresight-cpu-debug 850000.debug: EDPRSR: 00000001 (Power:On DLK:Unlock)
185 coresight-cpu-debug 850000.debug: EDPCSR: handle_IPI+0x174/0x1d8
186 coresight-cpu-debug 850000.debug: EDCIDSR: 00000000
187 …coresight-cpu-debug 850000.debug: EDVIDSR: 90000000 (State:Non-secure Mode:EL1/0 Width:64bits VMI…
188 coresight-cpu-debug 852000.debug: CPU[1]:
[all …]
H A Dcoresight-ect.rst4 CoreSight Embedded Cross Trigger (CTI & CTM).
13 The CoreSight Cross Trigger Interface (CTI) is a hardware device that takes
41 CoreSight devices on the trace data path. When these devices are enabled the
50 The hardware trigger signals can also be connected to non-CoreSight devices
62 The CTI devices appear on the existing CoreSight bus alongside the other
63 CoreSight devices::
65 >$ ls /sys/bus/coresight/devices
71 can be associated with other CoreSight devices, or other system hardware
74 >$ ls /sys/bus/coresight/devices/etm0/cti_cpu0
91 * ``mgmt``: the standard CoreSight management registers.
[all …]
/OK3568_Linux_fs/kernel/drivers/hwtracing/coresight/mali/
H A Dcoresight_mali_common.h28 /* Macros for CoreSight OP types. */
91 * struct coresight_mali_drvdata - Coresight mali driver data
93 * @csdev: Coresight device pointer
95 * @kbase_client: Pointer to coresight mali client
96 * @config: Pointer to coresight mali config, used for enabling and
97 * disabling the coresight component
98 * @enable_seq: Enable sequence needed to enable coresight block
99 * @disable_seq: Disable sequence needed to enable coresight block
115 * coresight_mali_enable_component - Generic enable for a coresight block
117 * @csdev: Coresight device to be enabled
[all …]
/OK3568_Linux_fs/kernel/arch/arm/boot/dts/
H A Dhip04.dtsi272 compatible = "arm,coresight-etb10", "arm,primecell";
287 compatible = "arm,coresight-etb10", "arm,primecell";
302 compatible = "arm,coresight-etb10", "arm,primecell";
317 compatible = "arm,coresight-etb10", "arm,primecell";
332 compatible = "arm,coresight-tpiu", "arm,primecell";
350 compatible = "arm,coresight-static-replicator";
385 compatible = "arm,coresight-static-replicator";
420 compatible = "arm,coresight-static-replicator";
454 compatible = "arm,coresight-static-replicator";
485 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
[all …]
/OK3568_Linux_fs/kernel/drivers/acpi/
H A Dacpi_amba.c24 {"ARMHC500", 0}, /* ARM CoreSight ETM4x */
25 {"ARMHC501", 0}, /* ARM CoreSight ETR */
26 {"ARMHC502", 0}, /* ARM CoreSight STM */
27 {"ARMHC503", 0}, /* ARM CoreSight Debug */
28 {"ARMHC979", 0}, /* ARM CoreSight TPIU */
29 {"ARMHC97C", 0}, /* ARM CoreSight SoC-400 TMC, SoC-600 ETF/ETB */
30 {"ARMHC98D", 0}, /* ARM CoreSight Dynamic Replicator */
31 {"ARMHC9CA", 0}, /* ARM CoreSight CATU */
32 {"ARMHC9FF", 0}, /* ARM CoreSight Dynamic Funnel */

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