xref: /OK3568_Linux_fs/kernel/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593SmuzhiyunWhat:		/sys/bus/coresight/devices/etm<N>/enable_source
2*4882a593SmuzhiyunDate:		April 2015
3*4882a593SmuzhiyunKernelVersion:  4.01
4*4882a593SmuzhiyunContact:        Mathieu Poirier <mathieu.poirier@linaro.org>
5*4882a593SmuzhiyunDescription:	(RW) Enable/disable tracing on this specific trace entiry.
6*4882a593Smuzhiyun		Enabling a source implies the source has been configured
7*4882a593Smuzhiyun		properly and a sink has been identidifed for it.  The path
8*4882a593Smuzhiyun		of coresight components linking the source to the sink is
9*4882a593Smuzhiyun		configured and managed automatically by the coresight framework.
10*4882a593Smuzhiyun
11*4882a593SmuzhiyunWhat:		/sys/bus/coresight/devices/etm<N>/cpu
12*4882a593SmuzhiyunDate:		April 2015
13*4882a593SmuzhiyunKernelVersion:	4.01
14*4882a593SmuzhiyunContact:	Mathieu Poirier <mathieu.poirier@linaro.org>
15*4882a593SmuzhiyunDescription:	(Read) The CPU this tracing entity is associated with.
16*4882a593Smuzhiyun
17*4882a593SmuzhiyunWhat:		/sys/bus/coresight/devices/etm<N>/nr_pe_cmp
18*4882a593SmuzhiyunDate:		April 2015
19*4882a593SmuzhiyunKernelVersion:	4.01
20*4882a593SmuzhiyunContact:	Mathieu Poirier <mathieu.poirier@linaro.org>
21*4882a593SmuzhiyunDescription:	(Read) Indicates the number of PE comparator inputs that are
22*4882a593Smuzhiyun		available for tracing.
23*4882a593Smuzhiyun
24*4882a593SmuzhiyunWhat:		/sys/bus/coresight/devices/etm<N>/nr_addr_cmp
25*4882a593SmuzhiyunDate:		April 2015
26*4882a593SmuzhiyunKernelVersion:	4.01
27*4882a593SmuzhiyunContact:	Mathieu Poirier <mathieu.poirier@linaro.org>
28*4882a593SmuzhiyunDescription:	(Read) Indicates the number of address comparator pairs that are
29*4882a593Smuzhiyun		available for tracing.
30*4882a593Smuzhiyun
31*4882a593SmuzhiyunWhat:		/sys/bus/coresight/devices/etm<N>/nr_cntr
32*4882a593SmuzhiyunDate:		April 2015
33*4882a593SmuzhiyunKernelVersion:	4.01
34*4882a593SmuzhiyunContact:	Mathieu Poirier <mathieu.poirier@linaro.org>
35*4882a593SmuzhiyunDescription:	(Read) Indicates the number of counters that are available for
36*4882a593Smuzhiyun		tracing.
37*4882a593Smuzhiyun
38*4882a593SmuzhiyunWhat:		/sys/bus/coresight/devices/etm<N>/nr_ext_inp
39*4882a593SmuzhiyunDate:		April 2015
40*4882a593SmuzhiyunKernelVersion:	4.01
41*4882a593SmuzhiyunContact:	Mathieu Poirier <mathieu.poirier@linaro.org>
42*4882a593SmuzhiyunDescription:	(Read) Indicates how many external inputs are implemented.
43*4882a593Smuzhiyun
44*4882a593SmuzhiyunWhat:		/sys/bus/coresight/devices/etm<N>/numcidc
45*4882a593SmuzhiyunDate:		April 2015
46*4882a593SmuzhiyunKernelVersion:	4.01
47*4882a593SmuzhiyunContact:	Mathieu Poirier <mathieu.poirier@linaro.org>
48*4882a593SmuzhiyunDescription:	(Read) Indicates the number of Context ID comparators that are
49*4882a593Smuzhiyun		available for tracing.
50*4882a593Smuzhiyun
51*4882a593SmuzhiyunWhat:		/sys/bus/coresight/devices/etm<N>/numvmidc
52*4882a593SmuzhiyunDate:		April 2015
53*4882a593SmuzhiyunKernelVersion:	4.01
54*4882a593SmuzhiyunContact:	Mathieu Poirier <mathieu.poirier@linaro.org>
55*4882a593SmuzhiyunDescription:	(Read) Indicates the number of VMID comparators that are available
56*4882a593Smuzhiyun		for tracing.
57*4882a593Smuzhiyun
58*4882a593SmuzhiyunWhat:		/sys/bus/coresight/devices/etm<N>/nrseqstate
59*4882a593SmuzhiyunDate:		April 2015
60*4882a593SmuzhiyunKernelVersion:	4.01
61*4882a593SmuzhiyunContact:	Mathieu Poirier <mathieu.poirier@linaro.org>
62*4882a593SmuzhiyunDescription:	(Read) Indicates the number of sequencer states that are
63*4882a593Smuzhiyun		implemented.
64*4882a593Smuzhiyun
65*4882a593SmuzhiyunWhat:		/sys/bus/coresight/devices/etm<N>/nr_resource
66*4882a593SmuzhiyunDate:		April 2015
67*4882a593SmuzhiyunKernelVersion:	4.01
68*4882a593SmuzhiyunContact:	Mathieu Poirier <mathieu.poirier@linaro.org>
69*4882a593SmuzhiyunDescription:	(Read) Indicates the number of resource selection pairs that are
70*4882a593Smuzhiyun		available for tracing.
71*4882a593Smuzhiyun
72*4882a593SmuzhiyunWhat:		/sys/bus/coresight/devices/etm<N>/nr_ss_cmp
73*4882a593SmuzhiyunDate:		April 2015
74*4882a593SmuzhiyunKernelVersion:	4.01
75*4882a593SmuzhiyunContact:	Mathieu Poirier <mathieu.poirier@linaro.org>
76*4882a593SmuzhiyunDescription:	(Read) Indicates the number of single-shot comparator controls that
77*4882a593Smuzhiyun		are available for tracing.
78*4882a593Smuzhiyun
79*4882a593SmuzhiyunWhat:		/sys/bus/coresight/devices/etm<N>/reset
80*4882a593SmuzhiyunDate:		April 2015
81*4882a593SmuzhiyunKernelVersion:	4.01
82*4882a593SmuzhiyunContact:	Mathieu Poirier <mathieu.poirier@linaro.org>
83*4882a593SmuzhiyunDescription: 	(Write) Cancels all configuration on a trace unit and set it back
84*4882a593Smuzhiyun		to its boot configuration.
85*4882a593Smuzhiyun
86*4882a593SmuzhiyunWhat:		/sys/bus/coresight/devices/etm<N>/mode
87*4882a593SmuzhiyunDate:		April 2015
88*4882a593SmuzhiyunKernelVersion:	4.01
89*4882a593SmuzhiyunContact:	Mathieu Poirier <mathieu.poirier@linaro.org>
90*4882a593SmuzhiyunDescription: 	(RW) Controls various modes supported by this ETM, for example
91*4882a593Smuzhiyun		P0 instruction tracing, branch broadcast, cycle counting and
92*4882a593Smuzhiyun		context ID tracing.
93*4882a593Smuzhiyun
94*4882a593SmuzhiyunWhat:		/sys/bus/coresight/devices/etm<N>/pe
95*4882a593SmuzhiyunDate:		April 2015
96*4882a593SmuzhiyunKernelVersion:	4.01
97*4882a593SmuzhiyunContact:	Mathieu Poirier <mathieu.poirier@linaro.org>
98*4882a593SmuzhiyunDescription: 	(RW) Controls which PE to trace.
99*4882a593Smuzhiyun
100*4882a593SmuzhiyunWhat:		/sys/bus/coresight/devices/etm<N>/event
101*4882a593SmuzhiyunDate:		April 2015
102*4882a593SmuzhiyunKernelVersion:	4.01
103*4882a593SmuzhiyunContact:	Mathieu Poirier <mathieu.poirier@linaro.org>
104*4882a593SmuzhiyunDescription: 	(RW) Controls the tracing of arbitrary events from bank 0 to 3.
105*4882a593Smuzhiyun
106*4882a593SmuzhiyunWhat:		/sys/bus/coresight/devices/etm<N>/event_instren
107*4882a593SmuzhiyunDate:		April 2015
108*4882a593SmuzhiyunKernelVersion:	4.01
109*4882a593SmuzhiyunContact:	Mathieu Poirier <mathieu.poirier@linaro.org>
110*4882a593SmuzhiyunDescription: 	(RW) Controls the behavior of the events in bank 0 to 3.
111*4882a593Smuzhiyun
112*4882a593SmuzhiyunWhat:		/sys/bus/coresight/devices/etm<N>/event_ts
113*4882a593SmuzhiyunDate:		April 2015
114*4882a593SmuzhiyunKernelVersion:	4.01
115*4882a593SmuzhiyunContact:	Mathieu Poirier <mathieu.poirier@linaro.org>
116*4882a593SmuzhiyunDescription: 	(RW) Controls the insertion of global timestamps in the trace
117*4882a593Smuzhiyun		streams.
118*4882a593Smuzhiyun
119*4882a593SmuzhiyunWhat:		/sys/bus/coresight/devices/etm<N>/syncfreq
120*4882a593SmuzhiyunDate:		April 2015
121*4882a593SmuzhiyunKernelVersion:	4.01
122*4882a593SmuzhiyunContact:	Mathieu Poirier <mathieu.poirier@linaro.org>
123*4882a593SmuzhiyunDescription: 	(RW) Controls how often trace synchronization requests occur.
124*4882a593Smuzhiyun
125*4882a593SmuzhiyunWhat:		/sys/bus/coresight/devices/etm<N>/cyc_threshold
126*4882a593SmuzhiyunDate:		April 2015
127*4882a593SmuzhiyunKernelVersion:	4.01
128*4882a593SmuzhiyunContact:	Mathieu Poirier <mathieu.poirier@linaro.org>
129*4882a593SmuzhiyunDescription: 	(RW) Sets the threshold value for cycle counting.
130*4882a593Smuzhiyun
131*4882a593SmuzhiyunWhat:		/sys/bus/coresight/devices/etm<N>/bb_ctrl
132*4882a593SmuzhiyunDate:		April 2015
133*4882a593SmuzhiyunKernelVersion:	4.01
134*4882a593SmuzhiyunContact:	Mathieu Poirier <mathieu.poirier@linaro.org>
135*4882a593SmuzhiyunDescription: 	(RW) Controls which regions in the memory map are enabled to
136*4882a593Smuzhiyun		use branch broadcasting.
137*4882a593Smuzhiyun
138*4882a593SmuzhiyunWhat:		/sys/bus/coresight/devices/etm<N>/event_vinst
139*4882a593SmuzhiyunDate:		April 2015
140*4882a593SmuzhiyunKernelVersion:	4.01
141*4882a593SmuzhiyunContact:	Mathieu Poirier <mathieu.poirier@linaro.org>
142*4882a593SmuzhiyunDescription: 	(RW) Controls instruction trace filtering.
143*4882a593Smuzhiyun
144*4882a593SmuzhiyunWhat:		/sys/bus/coresight/devices/etm<N>/s_exlevel_vinst
145*4882a593SmuzhiyunDate:		April 2015
146*4882a593SmuzhiyunKernelVersion:	4.01
147*4882a593SmuzhiyunContact:	Mathieu Poirier <mathieu.poirier@linaro.org>
148*4882a593SmuzhiyunDescription: 	(RW) In Secure state, each bit controls whether instruction
149*4882a593Smuzhiyun		tracing is enabled for the corresponding exception level.
150*4882a593Smuzhiyun
151*4882a593SmuzhiyunWhat:		/sys/bus/coresight/devices/etm<N>/ns_exlevel_vinst
152*4882a593SmuzhiyunDate:		April 2015
153*4882a593SmuzhiyunKernelVersion:	4.01
154*4882a593SmuzhiyunContact:	Mathieu Poirier <mathieu.poirier@linaro.org>
155*4882a593SmuzhiyunDescription: 	(RW) In non-secure state, each bit controls whether instruction
156*4882a593Smuzhiyun		tracing is enabled for the corresponding exception level.
157*4882a593Smuzhiyun
158*4882a593SmuzhiyunWhat:		/sys/bus/coresight/devices/etm<N>/addr_idx
159*4882a593SmuzhiyunDate:		April 2015
160*4882a593SmuzhiyunKernelVersion:	4.01
161*4882a593SmuzhiyunContact:	Mathieu Poirier <mathieu.poirier@linaro.org>
162*4882a593SmuzhiyunDescription: 	(RW) Select which address comparator or pair (of comparators) to
163*4882a593Smuzhiyun		work with.
164*4882a593Smuzhiyun
165*4882a593SmuzhiyunWhat:		/sys/bus/coresight/devices/etm<N>/addr_instdatatype
166*4882a593SmuzhiyunDate:		April 2015
167*4882a593SmuzhiyunKernelVersion:	4.01
168*4882a593SmuzhiyunContact:	Mathieu Poirier <mathieu.poirier@linaro.org>
169*4882a593SmuzhiyunDescription: 	(RW) Controls what type of comparison the trace unit performs.
170*4882a593Smuzhiyun
171*4882a593SmuzhiyunWhat:		/sys/bus/coresight/devices/etm<N>/addr_single
172*4882a593SmuzhiyunDate:		April 2015
173*4882a593SmuzhiyunKernelVersion:	4.01
174*4882a593SmuzhiyunContact:	Mathieu Poirier <mathieu.poirier@linaro.org>
175*4882a593SmuzhiyunDescription: 	(RW) Used to setup single address comparator values.
176*4882a593Smuzhiyun
177*4882a593SmuzhiyunWhat:		/sys/bus/coresight/devices/etm<N>/addr_range
178*4882a593SmuzhiyunDate:		April 2015
179*4882a593SmuzhiyunKernelVersion:	4.01
180*4882a593SmuzhiyunContact:	Mathieu Poirier <mathieu.poirier@linaro.org>
181*4882a593SmuzhiyunDescription: 	(RW) Used to setup address range comparator values.
182*4882a593Smuzhiyun
183*4882a593SmuzhiyunWhat:		/sys/bus/coresight/devices/etm<N>/seq_idx
184*4882a593SmuzhiyunDate:		April 2015
185*4882a593SmuzhiyunKernelVersion:	4.01
186*4882a593SmuzhiyunContact:	Mathieu Poirier <mathieu.poirier@linaro.org>
187*4882a593SmuzhiyunDescription: 	(RW) Select which sequensor.
188*4882a593Smuzhiyun
189*4882a593SmuzhiyunWhat:		/sys/bus/coresight/devices/etm<N>/seq_state
190*4882a593SmuzhiyunDate:		April 2015
191*4882a593SmuzhiyunKernelVersion:	4.01
192*4882a593SmuzhiyunContact:	Mathieu Poirier <mathieu.poirier@linaro.org>
193*4882a593SmuzhiyunDescription: 	(RW) Use this to set, or read, the sequencer state.
194*4882a593Smuzhiyun
195*4882a593SmuzhiyunWhat:		/sys/bus/coresight/devices/etm<N>/seq_event
196*4882a593SmuzhiyunDate:		April 2015
197*4882a593SmuzhiyunKernelVersion:	4.01
198*4882a593SmuzhiyunContact:	Mathieu Poirier <mathieu.poirier@linaro.org>
199*4882a593SmuzhiyunDescription: 	(RW) Moves the sequencer state to a specific state.
200*4882a593Smuzhiyun
201*4882a593SmuzhiyunWhat:		/sys/bus/coresight/devices/etm<N>/seq_reset_event
202*4882a593SmuzhiyunDate:		April 2015
203*4882a593SmuzhiyunKernelVersion:	4.01
204*4882a593SmuzhiyunContact:	Mathieu Poirier <mathieu.poirier@linaro.org>
205*4882a593SmuzhiyunDescription: 	(RW) Moves the sequencer to state 0 when a programmed event
206*4882a593Smuzhiyun		occurs.
207*4882a593Smuzhiyun
208*4882a593SmuzhiyunWhat:		/sys/bus/coresight/devices/etm<N>/cntr_idx
209*4882a593SmuzhiyunDate:		April 2015
210*4882a593SmuzhiyunKernelVersion:	4.01
211*4882a593SmuzhiyunContact:	Mathieu Poirier <mathieu.poirier@linaro.org>
212*4882a593SmuzhiyunDescription: 	(RW) Select which counter unit to work with.
213*4882a593Smuzhiyun
214*4882a593SmuzhiyunWhat:		/sys/bus/coresight/devices/etm<N>/cntrldvr
215*4882a593SmuzhiyunDate:		April 2015
216*4882a593SmuzhiyunKernelVersion:	4.01
217*4882a593SmuzhiyunContact:	Mathieu Poirier <mathieu.poirier@linaro.org>
218*4882a593SmuzhiyunDescription: 	(RW) This sets or returns the reload count value of the
219*4882a593Smuzhiyun		specific counter.
220*4882a593Smuzhiyun
221*4882a593SmuzhiyunWhat:		/sys/bus/coresight/devices/etm<N>/cntr_val
222*4882a593SmuzhiyunDate:		April 2015
223*4882a593SmuzhiyunKernelVersion:	4.01
224*4882a593SmuzhiyunContact:	Mathieu Poirier <mathieu.poirier@linaro.org>
225*4882a593SmuzhiyunDescription: 	(RW) This sets or returns the current count value of the
226*4882a593Smuzhiyun                specific counter.
227*4882a593Smuzhiyun
228*4882a593SmuzhiyunWhat:		/sys/bus/coresight/devices/etm<N>/cntr_ctrl
229*4882a593SmuzhiyunDate:		April 2015
230*4882a593SmuzhiyunKernelVersion:	4.01
231*4882a593SmuzhiyunContact:	Mathieu Poirier <mathieu.poirier@linaro.org>
232*4882a593SmuzhiyunDescription: 	(RW) Controls the operation of the selected counter.
233*4882a593Smuzhiyun
234*4882a593SmuzhiyunWhat:		/sys/bus/coresight/devices/etm<N>/res_idx
235*4882a593SmuzhiyunDate:		April 2015
236*4882a593SmuzhiyunKernelVersion:	4.01
237*4882a593SmuzhiyunContact:	Mathieu Poirier <mathieu.poirier@linaro.org>
238*4882a593SmuzhiyunDescription: 	(RW) Select which resource selection unit to work with.
239*4882a593Smuzhiyun
240*4882a593SmuzhiyunWhat:		/sys/bus/coresight/devices/etm<N>/res_ctrl
241*4882a593SmuzhiyunDate:		April 2015
242*4882a593SmuzhiyunKernelVersion:	4.01
243*4882a593SmuzhiyunContact:	Mathieu Poirier <mathieu.poirier@linaro.org>
244*4882a593SmuzhiyunDescription: 	(RW) Controls the selection of the resources in the trace unit.
245*4882a593Smuzhiyun
246*4882a593SmuzhiyunWhat:		/sys/bus/coresight/devices/etm<N>/ctxid_idx
247*4882a593SmuzhiyunDate:		April 2015
248*4882a593SmuzhiyunKernelVersion:	4.01
249*4882a593SmuzhiyunContact:	Mathieu Poirier <mathieu.poirier@linaro.org>
250*4882a593SmuzhiyunDescription:	(RW) Select which context ID comparator to work with.
251*4882a593Smuzhiyun
252*4882a593SmuzhiyunWhat:		/sys/bus/coresight/devices/etm<N>/ctxid_pid
253*4882a593SmuzhiyunDate:		April 2015
254*4882a593SmuzhiyunKernelVersion:	4.01
255*4882a593SmuzhiyunContact:	Mathieu Poirier <mathieu.poirier@linaro.org>
256*4882a593SmuzhiyunDescription:	(RW) Get/Set the context ID comparator value to trigger on.
257*4882a593Smuzhiyun
258*4882a593SmuzhiyunWhat:		/sys/bus/coresight/devices/etm<N>/ctxid_masks
259*4882a593SmuzhiyunDate:		April 2015
260*4882a593SmuzhiyunKernelVersion:	4.01
261*4882a593SmuzhiyunContact:	Mathieu Poirier <mathieu.poirier@linaro.org>
262*4882a593SmuzhiyunDescription:	(RW) Mask for all 8 context ID comparator value
263*4882a593Smuzhiyun		registers (if implemented).
264*4882a593Smuzhiyun
265*4882a593SmuzhiyunWhat:		/sys/bus/coresight/devices/etm<N>/vmid_idx
266*4882a593SmuzhiyunDate:		April 2015
267*4882a593SmuzhiyunKernelVersion:	4.01
268*4882a593SmuzhiyunContact:	Mathieu Poirier <mathieu.poirier@linaro.org>
269*4882a593SmuzhiyunDescription:	(RW) Select which virtual machine ID comparator to work with.
270*4882a593Smuzhiyun
271*4882a593SmuzhiyunWhat:		/sys/bus/coresight/devices/etm<N>/vmid_val
272*4882a593SmuzhiyunDate:		April 2015
273*4882a593SmuzhiyunKernelVersion:	4.01
274*4882a593SmuzhiyunContact:	Mathieu Poirier <mathieu.poirier@linaro.org>
275*4882a593SmuzhiyunDescription:	(RW) Get/Set the virtual machine ID comparator value to
276*4882a593Smuzhiyun		trigger on.
277*4882a593Smuzhiyun
278*4882a593SmuzhiyunWhat:		/sys/bus/coresight/devices/etm<N>/vmid_masks
279*4882a593SmuzhiyunDate:		April 2015
280*4882a593SmuzhiyunKernelVersion:	4.01
281*4882a593SmuzhiyunContact:	Mathieu Poirier <mathieu.poirier@linaro.org>
282*4882a593SmuzhiyunDescription:	(RW) Mask for all 8 virtual machine ID comparator value
283*4882a593Smuzhiyun		registers (if implemented).
284*4882a593Smuzhiyun
285*4882a593SmuzhiyunWhat:		/sys/bus/coresight/devices/etm<N>/addr_exlevel_s_ns
286*4882a593SmuzhiyunDate:		December 2019
287*4882a593SmuzhiyunKernelVersion:	5.5
288*4882a593SmuzhiyunContact:	Mathieu Poirier <mathieu.poirier@linaro.org>
289*4882a593SmuzhiyunDescription:	(RW) Set the Exception Level matching bits for secure and
290*4882a593Smuzhiyun		non-secure exception levels.
291*4882a593Smuzhiyun
292*4882a593SmuzhiyunWhat:		/sys/bus/coresight/devices/etm<N>/vinst_pe_cmp_start_stop
293*4882a593SmuzhiyunDate:		December 2019
294*4882a593SmuzhiyunKernelVersion:	5.5
295*4882a593SmuzhiyunContact:	Mathieu Poirier <mathieu.poirier@linaro.org>
296*4882a593SmuzhiyunDescription:	(RW) Access the start stop control register for PE input
297*4882a593Smuzhiyun		comparators.
298*4882a593Smuzhiyun
299*4882a593SmuzhiyunWhat:		/sys/bus/coresight/devices/etm<N>/addr_cmp_view
300*4882a593SmuzhiyunDate:		December 2019
301*4882a593SmuzhiyunKernelVersion:	5.5
302*4882a593SmuzhiyunContact:	Mathieu Poirier <mathieu.poirier@linaro.org>
303*4882a593SmuzhiyunDescription:	(Read) Print the current settings for the selected address
304*4882a593Smuzhiyun		comparator.
305*4882a593Smuzhiyun
306*4882a593SmuzhiyunWhat:		/sys/bus/coresight/devices/etm<N>/sshot_idx
307*4882a593SmuzhiyunDate:		December 2019
308*4882a593SmuzhiyunKernelVersion:	5.5
309*4882a593SmuzhiyunContact:	Mathieu Poirier <mathieu.poirier@linaro.org>
310*4882a593SmuzhiyunDescription:	(RW) Select the single shot control register to access.
311*4882a593Smuzhiyun
312*4882a593SmuzhiyunWhat:		/sys/bus/coresight/devices/etm<N>/sshot_ctrl
313*4882a593SmuzhiyunDate:		December 2019
314*4882a593SmuzhiyunKernelVersion:	5.5
315*4882a593SmuzhiyunContact:	Mathieu Poirier <mathieu.poirier@linaro.org>
316*4882a593SmuzhiyunDescription:	(RW) Access the selected single shot control register.
317*4882a593Smuzhiyun
318*4882a593SmuzhiyunWhat:		/sys/bus/coresight/devices/etm<N>/sshot_status
319*4882a593SmuzhiyunDate:		December 2019
320*4882a593SmuzhiyunKernelVersion:	5.5
321*4882a593SmuzhiyunContact:	Mathieu Poirier <mathieu.poirier@linaro.org>
322*4882a593SmuzhiyunDescription:	(Read) Print the current value of the selected single shot
323*4882a593Smuzhiyun		status register.
324*4882a593Smuzhiyun
325*4882a593SmuzhiyunWhat:		/sys/bus/coresight/devices/etm<N>/sshot_pe_ctrl
326*4882a593SmuzhiyunDate:		December 2019
327*4882a593SmuzhiyunKernelVersion:	5.5
328*4882a593SmuzhiyunContact:	Mathieu Poirier <mathieu.poirier@linaro.org>
329*4882a593SmuzhiyunDescription:	(RW) Access the selected single show PE comparator control
330*4882a593Smuzhiyun		register.
331*4882a593Smuzhiyun
332*4882a593SmuzhiyunWhat:		/sys/bus/coresight/devices/etm<N>/mgmt/trcoslsr
333*4882a593SmuzhiyunDate:		April 2015
334*4882a593SmuzhiyunKernelVersion:	4.01
335*4882a593SmuzhiyunContact:	Mathieu Poirier <mathieu.poirier@linaro.org>
336*4882a593SmuzhiyunDescription:	(Read) Print the content of the OS Lock Status Register (0x304).
337*4882a593Smuzhiyun		The value it taken directly  from the HW.
338*4882a593Smuzhiyun
339*4882a593SmuzhiyunWhat:		/sys/bus/coresight/devices/etm<N>/mgmt/trcpdcr
340*4882a593SmuzhiyunDate:		April 2015
341*4882a593SmuzhiyunKernelVersion:	4.01
342*4882a593SmuzhiyunContact:	Mathieu Poirier <mathieu.poirier@linaro.org>
343*4882a593SmuzhiyunDescription:	(Read) Print the content of the Power Down Control Register
344*4882a593Smuzhiyun		(0x310).  The value is taken directly from the HW.
345*4882a593Smuzhiyun
346*4882a593SmuzhiyunWhat:		/sys/bus/coresight/devices/etm<N>/mgmt/trcpdsr
347*4882a593SmuzhiyunDate:		April 2015
348*4882a593SmuzhiyunKernelVersion:	4.01
349*4882a593SmuzhiyunContact:	Mathieu Poirier <mathieu.poirier@linaro.org>
350*4882a593SmuzhiyunDescription:	(Read) Print the content of the Power Down Status Register
351*4882a593Smuzhiyun		(0x314).  The value is taken directly from the HW.
352*4882a593Smuzhiyun
353*4882a593SmuzhiyunWhat:		/sys/bus/coresight/devices/etm<N>/mgmt/trclsr
354*4882a593SmuzhiyunDate:		April 2015
355*4882a593SmuzhiyunKernelVersion:	4.01
356*4882a593SmuzhiyunContact:	Mathieu Poirier <mathieu.poirier@linaro.org>
357*4882a593SmuzhiyunDescription:	(Read) Print the content of the SW Lock Status Register
358*4882a593Smuzhiyun		(0xFB4).  The value is taken directly from the HW.
359*4882a593Smuzhiyun
360*4882a593SmuzhiyunWhat:		/sys/bus/coresight/devices/etm<N>/mgmt/trcauthstatus
361*4882a593SmuzhiyunDate:		April 2015
362*4882a593SmuzhiyunKernelVersion:	4.01
363*4882a593SmuzhiyunContact:	Mathieu Poirier <mathieu.poirier@linaro.org>
364*4882a593SmuzhiyunDescription:	(Read) Print the content of the Authentication Status Register
365*4882a593Smuzhiyun		(0xFB8).  The value is taken directly from the HW.
366*4882a593Smuzhiyun
367*4882a593SmuzhiyunWhat:		/sys/bus/coresight/devices/etm<N>/mgmt/trcdevid
368*4882a593SmuzhiyunDate:		April 2015
369*4882a593SmuzhiyunKernelVersion:	4.01
370*4882a593SmuzhiyunContact:	Mathieu Poirier <mathieu.poirier@linaro.org>
371*4882a593SmuzhiyunDescription:	(Read) Print the content of the Device ID Register
372*4882a593Smuzhiyun		(0xFC8).  The value is taken directly from the HW.
373*4882a593Smuzhiyun
374*4882a593SmuzhiyunWhat:		/sys/bus/coresight/devices/etm<N>/mgmt/trcdevarch
375*4882a593SmuzhiyunDate:		January 2021
376*4882a593SmuzhiyunKernelVersion:	5.12
377*4882a593SmuzhiyunContact:	Mathieu Poirier <mathieu.poirier@linaro.org>
378*4882a593SmuzhiyunDescription:	(Read) Print the content of the Device Architecture Register
379*4882a593Smuzhiyun		(offset 0xFBC).  The value is taken directly read
380*4882a593Smuzhiyun		from the HW.
381*4882a593Smuzhiyun
382*4882a593SmuzhiyunWhat:		/sys/bus/coresight/devices/etm<N>/mgmt/trcdevtype
383*4882a593SmuzhiyunDate:		April 2015
384*4882a593SmuzhiyunKernelVersion:	4.01
385*4882a593SmuzhiyunContact:	Mathieu Poirier <mathieu.poirier@linaro.org>
386*4882a593SmuzhiyunDescription:	(Read) Print the content of the Device Type Register
387*4882a593Smuzhiyun		(0xFCC).  The value is taken directly from the HW.
388*4882a593Smuzhiyun
389*4882a593SmuzhiyunWhat:		/sys/bus/coresight/devices/etm<N>/mgmt/trcpidr0
390*4882a593SmuzhiyunDate:		April 2015
391*4882a593SmuzhiyunKernelVersion:	4.01
392*4882a593SmuzhiyunContact:	Mathieu Poirier <mathieu.poirier@linaro.org>
393*4882a593SmuzhiyunDescription:	(Read) Print the content of the Peripheral ID0 Register
394*4882a593Smuzhiyun		(0xFE0).  The value is taken directly from the HW.
395*4882a593Smuzhiyun
396*4882a593SmuzhiyunWhat:		/sys/bus/coresight/devices/etm<N>/mgmt/trcpidr1
397*4882a593SmuzhiyunDate:		April 2015
398*4882a593SmuzhiyunKernelVersion:	4.01
399*4882a593SmuzhiyunContact:	Mathieu Poirier <mathieu.poirier@linaro.org>
400*4882a593SmuzhiyunDescription:	(Read) Print the content of the Peripheral ID1 Register
401*4882a593Smuzhiyun		(0xFE4).  The value is taken directly from the HW.
402*4882a593Smuzhiyun
403*4882a593SmuzhiyunWhat:		/sys/bus/coresight/devices/etm<N>/mgmt/trcpidr2
404*4882a593SmuzhiyunDate:		April 2015
405*4882a593SmuzhiyunKernelVersion:	4.01
406*4882a593SmuzhiyunContact:	Mathieu Poirier <mathieu.poirier@linaro.org>
407*4882a593SmuzhiyunDescription:	(Read) Print the content of the Peripheral ID2 Register
408*4882a593Smuzhiyun		(0xFE8).  The value is taken directly from the HW.
409*4882a593Smuzhiyun
410*4882a593SmuzhiyunWhat:		/sys/bus/coresight/devices/etm<N>/mgmt/trcpidr3
411*4882a593SmuzhiyunDate:		April 2015
412*4882a593SmuzhiyunKernelVersion:	4.01
413*4882a593SmuzhiyunContact:	Mathieu Poirier <mathieu.poirier@linaro.org>
414*4882a593SmuzhiyunDescription:	(Read) Print the content of the Peripheral ID3 Register
415*4882a593Smuzhiyun		(0xFEC).  The value is taken directly from the HW.
416*4882a593Smuzhiyun
417*4882a593SmuzhiyunWhat:		/sys/bus/coresight/devices/etm<N>/mgmt/trcconfig
418*4882a593SmuzhiyunDate:		February 2016
419*4882a593SmuzhiyunKernelVersion:	4.07
420*4882a593SmuzhiyunContact:	Mathieu Poirier <mathieu.poirier@linaro.org>
421*4882a593SmuzhiyunDescription:	(Read) Print the content of the trace configuration register
422*4882a593Smuzhiyun		(0x010) as currently set by SW.
423*4882a593Smuzhiyun
424*4882a593SmuzhiyunWhat:		/sys/bus/coresight/devices/etm<N>/mgmt/trctraceid
425*4882a593SmuzhiyunDate:		February 2016
426*4882a593SmuzhiyunKernelVersion:	4.07
427*4882a593SmuzhiyunContact:	Mathieu Poirier <mathieu.poirier@linaro.org>
428*4882a593SmuzhiyunDescription:	(Read) Print the content of the trace ID register (0x040).
429*4882a593Smuzhiyun
430*4882a593SmuzhiyunWhat:		/sys/bus/coresight/devices/etm<N>/trcidr/trcidr0
431*4882a593SmuzhiyunDate:		April 2015
432*4882a593SmuzhiyunKernelVersion:	4.01
433*4882a593SmuzhiyunContact:	Mathieu Poirier <mathieu.poirier@linaro.org>
434*4882a593SmuzhiyunDescription:	(Read) Returns the tracing capabilities of the trace unit (0x1E0).
435*4882a593Smuzhiyun		The value is taken directly from the HW.
436*4882a593Smuzhiyun
437*4882a593SmuzhiyunWhat:		/sys/bus/coresight/devices/etm<N>/trcidr/trcidr1
438*4882a593SmuzhiyunDate:		April 2015
439*4882a593SmuzhiyunKernelVersion:	4.01
440*4882a593SmuzhiyunContact:	Mathieu Poirier <mathieu.poirier@linaro.org>
441*4882a593SmuzhiyunDescription:	(Read) Returns the tracing capabilities of the trace unit (0x1E4).
442*4882a593Smuzhiyun		The value is taken directly from the HW.
443*4882a593Smuzhiyun
444*4882a593SmuzhiyunWhat:		/sys/bus/coresight/devices/etm<N>/trcidr/trcidr2
445*4882a593SmuzhiyunDate:		April 2015
446*4882a593SmuzhiyunKernelVersion:	4.01
447*4882a593SmuzhiyunContact:	Mathieu Poirier <mathieu.poirier@linaro.org>
448*4882a593SmuzhiyunDescription:	(Read) Returns the maximum size of the data value, data address,
449*4882a593Smuzhiyun		VMID, context ID and instuction address in the trace unit
450*4882a593Smuzhiyun		(0x1E8).  The value is taken directly from the HW.
451*4882a593Smuzhiyun
452*4882a593SmuzhiyunWhat:		/sys/bus/coresight/devices/etm<N>/trcidr/trcidr3
453*4882a593SmuzhiyunDate:		April 2015
454*4882a593SmuzhiyunKernelVersion:	4.01
455*4882a593SmuzhiyunContact:	Mathieu Poirier <mathieu.poirier@linaro.org>
456*4882a593SmuzhiyunDescription:	(Read) Returns the value associated with various resources
457*4882a593Smuzhiyun		available to the trace unit.  See the Trace Macrocell
458*4882a593Smuzhiyun		architecture specification for more details (0x1E8).
459*4882a593Smuzhiyun		The value is taken directly from the HW.
460*4882a593Smuzhiyun
461*4882a593SmuzhiyunWhat:		/sys/bus/coresight/devices/etm<N>/trcidr/trcidr4
462*4882a593SmuzhiyunDate:		April 2015
463*4882a593SmuzhiyunKernelVersion:	4.01
464*4882a593SmuzhiyunContact:	Mathieu Poirier <mathieu.poirier@linaro.org>
465*4882a593SmuzhiyunDescription:	(Read) Returns how many resources the trace unit supports (0x1F0).
466*4882a593Smuzhiyun		The value is taken directly from the HW.
467*4882a593Smuzhiyun
468*4882a593SmuzhiyunWhat:		/sys/bus/coresight/devices/etm<N>/trcidr/trcidr5
469*4882a593SmuzhiyunDate:		April 2015
470*4882a593SmuzhiyunKernelVersion:	4.01
471*4882a593SmuzhiyunContact:	Mathieu Poirier <mathieu.poirier@linaro.org>
472*4882a593SmuzhiyunDescription:	(Read) Returns how many resources the trace unit supports (0x1F4).
473*4882a593Smuzhiyun		The value is taken directly from the HW.
474*4882a593Smuzhiyun
475*4882a593SmuzhiyunWhat:		/sys/bus/coresight/devices/etm<N>/trcidr/trcidr8
476*4882a593SmuzhiyunDate:		April 2015
477*4882a593SmuzhiyunKernelVersion:	4.01
478*4882a593SmuzhiyunContact:	Mathieu Poirier <mathieu.poirier@linaro.org>
479*4882a593SmuzhiyunDescription:	(Read) Returns the maximum speculation depth of the instruction
480*4882a593Smuzhiyun		trace stream. (0x180).  The value is taken directly from the HW.
481*4882a593Smuzhiyun
482*4882a593SmuzhiyunWhat:		/sys/bus/coresight/devices/etm<N>/trcidr/trcidr9
483*4882a593SmuzhiyunDate:		April 2015
484*4882a593SmuzhiyunKernelVersion:	4.01
485*4882a593SmuzhiyunContact:	Mathieu Poirier <mathieu.poirier@linaro.org>
486*4882a593SmuzhiyunDescription:	(Read) Returns the number of P0 right-hand keys that the trace unit
487*4882a593Smuzhiyun		can use (0x184).  The value is taken directly from the HW.
488*4882a593Smuzhiyun
489*4882a593SmuzhiyunWhat:		/sys/bus/coresight/devices/etm<N>/trcidr/trcidr10
490*4882a593SmuzhiyunDate:		April 2015
491*4882a593SmuzhiyunKernelVersion:	4.01
492*4882a593SmuzhiyunContact:	Mathieu Poirier <mathieu.poirier@linaro.org>
493*4882a593SmuzhiyunDescription:	(Read) Returns the number of P1 right-hand keys that the trace unit
494*4882a593Smuzhiyun		can use (0x188).  The value is taken directly from the HW.
495*4882a593Smuzhiyun
496*4882a593SmuzhiyunWhat:		/sys/bus/coresight/devices/etm<N>/trcidr/trcidr11
497*4882a593SmuzhiyunDate:		April 2015
498*4882a593SmuzhiyunKernelVersion:	4.01
499*4882a593SmuzhiyunContact:	Mathieu Poirier <mathieu.poirier@linaro.org>
500*4882a593SmuzhiyunDescription:	(Read) Returns the number of special P1 right-hand keys that the
501*4882a593Smuzhiyun		trace unit can use (0x18C).  The value is taken directly from
502*4882a593Smuzhiyun		the HW.
503*4882a593Smuzhiyun
504*4882a593SmuzhiyunWhat:		/sys/bus/coresight/devices/etm<N>/trcidr/trcidr12
505*4882a593SmuzhiyunDate:		April 2015
506*4882a593SmuzhiyunKernelVersion:	4.01
507*4882a593SmuzhiyunContact:	Mathieu Poirier <mathieu.poirier@linaro.org>
508*4882a593SmuzhiyunDescription:	(Read) Returns the number of conditional P1 right-hand keys that
509*4882a593Smuzhiyun		the trace unit can use (0x190).  The value is taken directly
510*4882a593Smuzhiyun		from the HW.
511*4882a593Smuzhiyun
512*4882a593SmuzhiyunWhat:		/sys/bus/coresight/devices/etm<N>/trcidr/trcidr13
513*4882a593SmuzhiyunDate:		April 2015
514*4882a593SmuzhiyunKernelVersion:	4.01
515*4882a593SmuzhiyunContact:	Mathieu Poirier <mathieu.poirier@linaro.org>
516*4882a593SmuzhiyunDescription:	(Read) Returns the number of special conditional P1 right-hand keys
517*4882a593Smuzhiyun		that the trace unit can use (0x194).  The value is taken
518*4882a593Smuzhiyun		directly from the HW.
519