1*4882a593SmuzhiyunWhat: /sys/bus/coresight/devices/<memory_map>.etb/enable_sink 2*4882a593SmuzhiyunDate: November 2014 3*4882a593SmuzhiyunKernelVersion: 3.19 4*4882a593SmuzhiyunContact: Mathieu Poirier <mathieu.poirier@linaro.org> 5*4882a593SmuzhiyunDescription: (RW) Add/remove a sink from a trace path. There can be multiple 6*4882a593Smuzhiyun source for a single sink. 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun ex:: 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun echo 1 > /sys/bus/coresight/devices/20010000.etb/enable_sink 11*4882a593Smuzhiyun 12*4882a593SmuzhiyunWhat: /sys/bus/coresight/devices/<memory_map>.etb/trigger_cntr 13*4882a593SmuzhiyunDate: November 2014 14*4882a593SmuzhiyunKernelVersion: 3.19 15*4882a593SmuzhiyunContact: Mathieu Poirier <mathieu.poirier@linaro.org> 16*4882a593SmuzhiyunDescription: (RW) Disables write access to the Trace RAM by stopping the 17*4882a593Smuzhiyun formatter after a defined number of words have been stored 18*4882a593Smuzhiyun following the trigger event. The number of 32-bit words written 19*4882a593Smuzhiyun into the Trace RAM following the trigger event is equal to the 20*4882a593Smuzhiyun value stored in this register+1 (from ARM ETB-TRM). 21*4882a593Smuzhiyun 22*4882a593SmuzhiyunWhat: /sys/bus/coresight/devices/<memory_map>.etb/mgmt/rdp 23*4882a593SmuzhiyunDate: March 2016 24*4882a593SmuzhiyunKernelVersion: 4.7 25*4882a593SmuzhiyunContact: Mathieu Poirier <mathieu.poirier@linaro.org> 26*4882a593SmuzhiyunDescription: (Read) Defines the depth, in words, of the trace RAM in powers of 27*4882a593Smuzhiyun 2. The value is read directly from HW register RDP, 0x004. 28*4882a593Smuzhiyun 29*4882a593SmuzhiyunWhat: /sys/bus/coresight/devices/<memory_map>.etb/mgmt/sts 30*4882a593SmuzhiyunDate: March 2016 31*4882a593SmuzhiyunKernelVersion: 4.7 32*4882a593SmuzhiyunContact: Mathieu Poirier <mathieu.poirier@linaro.org> 33*4882a593SmuzhiyunDescription: (Read) Shows the value held by the ETB status register. The value 34*4882a593Smuzhiyun is read directly from HW register STS, 0x00C. 35*4882a593Smuzhiyun 36*4882a593SmuzhiyunWhat: /sys/bus/coresight/devices/<memory_map>.etb/mgmt/rrp 37*4882a593SmuzhiyunDate: March 2016 38*4882a593SmuzhiyunKernelVersion: 4.7 39*4882a593SmuzhiyunContact: Mathieu Poirier <mathieu.poirier@linaro.org> 40*4882a593SmuzhiyunDescription: (Read) Shows the value held by the ETB RAM Read Pointer register 41*4882a593Smuzhiyun that is used to read entries from the Trace RAM over the APB 42*4882a593Smuzhiyun interface. The value is read directly from HW register RRP, 43*4882a593Smuzhiyun 0x014. 44*4882a593Smuzhiyun 45*4882a593SmuzhiyunWhat: /sys/bus/coresight/devices/<memory_map>.etb/mgmt/rwp 46*4882a593SmuzhiyunDate: March 2016 47*4882a593SmuzhiyunKernelVersion: 4.7 48*4882a593SmuzhiyunContact: Mathieu Poirier <mathieu.poirier@linaro.org> 49*4882a593SmuzhiyunDescription: (Read) Shows the value held by the ETB RAM Write Pointer register 50*4882a593Smuzhiyun that is used to sets the write pointer to write entries from 51*4882a593Smuzhiyun the CoreSight bus into the Trace RAM. The value is read directly 52*4882a593Smuzhiyun from HW register RWP, 0x018. 53*4882a593Smuzhiyun 54*4882a593SmuzhiyunWhat: /sys/bus/coresight/devices/<memory_map>.etb/mgmt/trg 55*4882a593SmuzhiyunDate: March 2016 56*4882a593SmuzhiyunKernelVersion: 4.7 57*4882a593SmuzhiyunContact: Mathieu Poirier <mathieu.poirier@linaro.org> 58*4882a593SmuzhiyunDescription: (Read) Similar to "trigger_cntr" above except that this value is 59*4882a593Smuzhiyun read directly from HW register TRG, 0x01C. 60*4882a593Smuzhiyun 61*4882a593SmuzhiyunWhat: /sys/bus/coresight/devices/<memory_map>.etb/mgmt/ctl 62*4882a593SmuzhiyunDate: March 2016 63*4882a593SmuzhiyunKernelVersion: 4.7 64*4882a593SmuzhiyunContact: Mathieu Poirier <mathieu.poirier@linaro.org> 65*4882a593SmuzhiyunDescription: (Read) Shows the value held by the ETB Control register. The value 66*4882a593Smuzhiyun is read directly from HW register CTL, 0x020. 67*4882a593Smuzhiyun 68*4882a593SmuzhiyunWhat: /sys/bus/coresight/devices/<memory_map>.etb/mgmt/ffsr 69*4882a593SmuzhiyunDate: March 2016 70*4882a593SmuzhiyunKernelVersion: 4.7 71*4882a593SmuzhiyunContact: Mathieu Poirier <mathieu.poirier@linaro.org> 72*4882a593SmuzhiyunDescription: (Read) Shows the value held by the ETB Formatter and Flush Status 73*4882a593Smuzhiyun register. The value is read directly from HW register FFSR, 74*4882a593Smuzhiyun 0x300. 75*4882a593Smuzhiyun 76*4882a593SmuzhiyunWhat: /sys/bus/coresight/devices/<memory_map>.etb/mgmt/ffcr 77*4882a593SmuzhiyunDate: March 2016 78*4882a593SmuzhiyunKernelVersion: 4.7 79*4882a593SmuzhiyunContact: Mathieu Poirier <mathieu.poirier@linaro.org> 80*4882a593SmuzhiyunDescription: (Read) Shows the value held by the ETB Formatter and Flush Control 81*4882a593Smuzhiyun register. The value is read directly from HW register FFCR, 82*4882a593Smuzhiyun 0x304. 83