1*4882a593SmuzhiyunWhat: /sys/bus/coresight/devices/<memory_map>.tmc/trigger_cntr 2*4882a593SmuzhiyunDate: November 2014 3*4882a593SmuzhiyunKernelVersion: 3.19 4*4882a593SmuzhiyunContact: Mathieu Poirier <mathieu.poirier@linaro.org> 5*4882a593SmuzhiyunDescription: (RW) Disables write access to the Trace RAM by stopping the 6*4882a593Smuzhiyun formatter after a defined number of words have been stored 7*4882a593Smuzhiyun following the trigger event. Additional interface for this 8*4882a593Smuzhiyun driver are expected to be added as it matures. 9*4882a593Smuzhiyun 10*4882a593SmuzhiyunWhat: /sys/bus/coresight/devices/<memory_map>.tmc/mgmt/rsz 11*4882a593SmuzhiyunDate: March 2016 12*4882a593SmuzhiyunKernelVersion: 4.7 13*4882a593SmuzhiyunContact: Mathieu Poirier <mathieu.poirier@linaro.org> 14*4882a593SmuzhiyunDescription: (Read) Defines the size, in 32-bit words, of the local RAM buffer. 15*4882a593Smuzhiyun The value is read directly from HW register RSZ, 0x004. 16*4882a593Smuzhiyun 17*4882a593SmuzhiyunWhat: /sys/bus/coresight/devices/<memory_map>.tmc/mgmt/sts 18*4882a593SmuzhiyunDate: March 2016 19*4882a593SmuzhiyunKernelVersion: 4.7 20*4882a593SmuzhiyunContact: Mathieu Poirier <mathieu.poirier@linaro.org> 21*4882a593SmuzhiyunDescription: (Read) Shows the value held by the TMC status register. The value 22*4882a593Smuzhiyun is read directly from HW register STS, 0x00C. 23*4882a593Smuzhiyun 24*4882a593SmuzhiyunWhat: /sys/bus/coresight/devices/<memory_map>.tmc/mgmt/rrp 25*4882a593SmuzhiyunDate: March 2016 26*4882a593SmuzhiyunKernelVersion: 4.7 27*4882a593SmuzhiyunContact: Mathieu Poirier <mathieu.poirier@linaro.org> 28*4882a593SmuzhiyunDescription: (Read) Shows the value held by the TMC RAM Read Pointer register 29*4882a593Smuzhiyun that is used to read entries from the Trace RAM over the APB 30*4882a593Smuzhiyun interface. The value is read directly from HW register RRP, 31*4882a593Smuzhiyun 0x014. 32*4882a593Smuzhiyun 33*4882a593SmuzhiyunWhat: /sys/bus/coresight/devices/<memory_map>.tmc/mgmt/rwp 34*4882a593SmuzhiyunDate: March 2016 35*4882a593SmuzhiyunKernelVersion: 4.7 36*4882a593SmuzhiyunContact: Mathieu Poirier <mathieu.poirier@linaro.org> 37*4882a593SmuzhiyunDescription: (Read) Shows the value held by the TMC RAM Write Pointer register 38*4882a593Smuzhiyun that is used to sets the write pointer to write entries from 39*4882a593Smuzhiyun the CoreSight bus into the Trace RAM. The value is read directly 40*4882a593Smuzhiyun from HW register RWP, 0x018. 41*4882a593Smuzhiyun 42*4882a593SmuzhiyunWhat: /sys/bus/coresight/devices/<memory_map>.tmc/mgmt/trg 43*4882a593SmuzhiyunDate: March 2016 44*4882a593SmuzhiyunKernelVersion: 4.7 45*4882a593SmuzhiyunContact: Mathieu Poirier <mathieu.poirier@linaro.org> 46*4882a593SmuzhiyunDescription: (Read) Similar to "trigger_cntr" above except that this value is 47*4882a593Smuzhiyun read directly from HW register TRG, 0x01C. 48*4882a593Smuzhiyun 49*4882a593SmuzhiyunWhat: /sys/bus/coresight/devices/<memory_map>.tmc/mgmt/ctl 50*4882a593SmuzhiyunDate: March 2016 51*4882a593SmuzhiyunKernelVersion: 4.7 52*4882a593SmuzhiyunContact: Mathieu Poirier <mathieu.poirier@linaro.org> 53*4882a593SmuzhiyunDescription: (Read) Shows the value held by the TMC Control register. The value 54*4882a593Smuzhiyun is read directly from HW register CTL, 0x020. 55*4882a593Smuzhiyun 56*4882a593SmuzhiyunWhat: /sys/bus/coresight/devices/<memory_map>.tmc/mgmt/ffsr 57*4882a593SmuzhiyunDate: March 2016 58*4882a593SmuzhiyunKernelVersion: 4.7 59*4882a593SmuzhiyunContact: Mathieu Poirier <mathieu.poirier@linaro.org> 60*4882a593SmuzhiyunDescription: (Read) Shows the value held by the TMC Formatter and Flush Status 61*4882a593Smuzhiyun register. The value is read directly from HW register FFSR, 62*4882a593Smuzhiyun 0x300. 63*4882a593Smuzhiyun 64*4882a593SmuzhiyunWhat: /sys/bus/coresight/devices/<memory_map>.tmc/mgmt/ffcr 65*4882a593SmuzhiyunDate: March 2016 66*4882a593SmuzhiyunKernelVersion: 4.7 67*4882a593SmuzhiyunContact: Mathieu Poirier <mathieu.poirier@linaro.org> 68*4882a593SmuzhiyunDescription: (Read) Shows the value held by the TMC Formatter and Flush Control 69*4882a593Smuzhiyun register. The value is read directly from HW register FFCR, 70*4882a593Smuzhiyun 0x304. 71*4882a593Smuzhiyun 72*4882a593SmuzhiyunWhat: /sys/bus/coresight/devices/<memory_map>.tmc/mgmt/mode 73*4882a593SmuzhiyunDate: March 2016 74*4882a593SmuzhiyunKernelVersion: 4.7 75*4882a593SmuzhiyunContact: Mathieu Poirier <mathieu.poirier@linaro.org> 76*4882a593SmuzhiyunDescription: (Read) Shows the value held by the TMC Mode register, which 77*4882a593Smuzhiyun indicate the mode the device has been configured to enact. The 78*4882a593Smuzhiyun The value is read directly from the MODE register, 0x028. 79*4882a593Smuzhiyun 80*4882a593SmuzhiyunWhat: /sys/bus/coresight/devices/<memory_map>.tmc/mgmt/devid 81*4882a593SmuzhiyunDate: March 2016 82*4882a593SmuzhiyunKernelVersion: 4.7 83*4882a593SmuzhiyunContact: Mathieu Poirier <mathieu.poirier@linaro.org> 84*4882a593SmuzhiyunDescription: (Read) Indicates the capabilities of the Coresight TMC. 85*4882a593Smuzhiyun The value is read directly from the DEVID register, 0xFC8, 86*4882a593Smuzhiyun 87*4882a593SmuzhiyunWhat: /sys/bus/coresight/devices/<memory_map>.tmc/buffer_size 88*4882a593SmuzhiyunDate: December 2018 89*4882a593SmuzhiyunKernelVersion: 4.19 90*4882a593SmuzhiyunContact: Mathieu Poirier <mathieu.poirier@linaro.org> 91*4882a593SmuzhiyunDescription: (RW) Size of the trace buffer for TMC-ETR when used in SYSFS 92*4882a593Smuzhiyun mode. Writable only for TMC-ETR configurations. The value 93*4882a593Smuzhiyun should be aligned to the kernel pagesize. 94