1*4882a593SmuzhiyunWhat: /sys/bus/coresight/devices/<memory_map>.stm/enable_source 2*4882a593SmuzhiyunDate: April 2016 3*4882a593SmuzhiyunKernelVersion: 4.7 4*4882a593SmuzhiyunContact: Mathieu Poirier <mathieu.poirier@linaro.org> 5*4882a593SmuzhiyunDescription: (RW) Enable/disable tracing on this specific trace macrocell. 6*4882a593Smuzhiyun Enabling the trace macrocell implies it has been configured 7*4882a593Smuzhiyun properly and a sink has been identified for it. The path 8*4882a593Smuzhiyun of coresight components linking the source to the sink is 9*4882a593Smuzhiyun configured and managed automatically by the coresight framework. 10*4882a593Smuzhiyun 11*4882a593SmuzhiyunWhat: /sys/bus/coresight/devices/<memory_map>.stm/hwevent_enable 12*4882a593SmuzhiyunDate: April 2016 13*4882a593SmuzhiyunKernelVersion: 4.7 14*4882a593SmuzhiyunContact: Mathieu Poirier <mathieu.poirier@linaro.org> 15*4882a593SmuzhiyunDescription: (RW) Provides access to the HW event enable register, used in 16*4882a593Smuzhiyun conjunction with HW event bank select register. 17*4882a593Smuzhiyun 18*4882a593SmuzhiyunWhat: /sys/bus/coresight/devices/<memory_map>.stm/hwevent_select 19*4882a593SmuzhiyunDate: April 2016 20*4882a593SmuzhiyunKernelVersion: 4.7 21*4882a593SmuzhiyunContact: Mathieu Poirier <mathieu.poirier@linaro.org> 22*4882a593SmuzhiyunDescription: (RW) Gives access to the HW event block select register 23*4882a593Smuzhiyun (STMHEBSR) in order to configure up to 256 channels. Used in 24*4882a593Smuzhiyun conjunction with "hwevent_enable" register as described above. 25*4882a593Smuzhiyun 26*4882a593SmuzhiyunWhat: /sys/bus/coresight/devices/<memory_map>.stm/port_enable 27*4882a593SmuzhiyunDate: April 2016 28*4882a593SmuzhiyunKernelVersion: 4.7 29*4882a593SmuzhiyunContact: Mathieu Poirier <mathieu.poirier@linaro.org> 30*4882a593SmuzhiyunDescription: (RW) Provides access to the stimulus port enable register 31*4882a593Smuzhiyun (STMSPER). Used in conjunction with "port_select" described 32*4882a593Smuzhiyun below. 33*4882a593Smuzhiyun 34*4882a593SmuzhiyunWhat: /sys/bus/coresight/devices/<memory_map>.stm/port_select 35*4882a593SmuzhiyunDate: April 2016 36*4882a593SmuzhiyunKernelVersion: 4.7 37*4882a593SmuzhiyunContact: Mathieu Poirier <mathieu.poirier@linaro.org> 38*4882a593SmuzhiyunDescription: (RW) Used to determine which bank of stimulus port bit in 39*4882a593Smuzhiyun register STMSPER (see above) apply to. 40*4882a593Smuzhiyun 41*4882a593SmuzhiyunWhat: /sys/bus/coresight/devices/<memory_map>.stm/status 42*4882a593SmuzhiyunDate: April 2016 43*4882a593SmuzhiyunKernelVersion: 4.7 44*4882a593SmuzhiyunContact: Mathieu Poirier <mathieu.poirier@linaro.org> 45*4882a593SmuzhiyunDescription: (Read) List various control and status registers. The specific 46*4882a593Smuzhiyun layout and content is driver specific. 47*4882a593Smuzhiyun 48*4882a593SmuzhiyunWhat: /sys/bus/coresight/devices/<memory_map>.stm/traceid 49*4882a593SmuzhiyunDate: April 2016 50*4882a593SmuzhiyunKernelVersion: 4.7 51*4882a593SmuzhiyunContact: Mathieu Poirier <mathieu.poirier@linaro.org> 52*4882a593SmuzhiyunDescription: (RW) Holds the trace ID that will appear in the trace stream 53*4882a593Smuzhiyun coming from this trace entity. 54